| 19bdabb5 | 31-Oct-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: kernel: main.c: implement tee_otp_get_hw_unique_key()
Sets the hardware unique key to zero. To model OTP device, Spike introduce the ability to write plugins in the form of shared object file
riscv: kernel: main.c: implement tee_otp_get_hw_unique_key()
Sets the hardware unique key to zero. To model OTP device, Spike introduce the ability to write plugins in the form of shared object files that allow user-defined Memory-Mapped-I/O behaviors.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 44588001 | 24-Oct-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: include: add core_mmu_arch.h
Add defines for MMU configuration and helper functions.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere
riscv: include: add core_mmu_arch.h
Add defines for MMU configuration and helper functions.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 6d816494 | 24-Oct-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: include: add thread_arch.h
Minimalist version which defines contexts registers structures and thread local structure. This to allow compiling for RISC-V architecture.
Signed-off-by: Marouene
riscv: include: add thread_arch.h
Minimalist version which defines contexts registers structures and thread local structure. This to allow compiling for RISC-V architecture.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| a92f3814 | 24-Oct-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: include: add cache_helpers_arch.h
Nothing to define for now.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 5f7b832a | 24-Oct-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: core: define CFG_MAX_CACHE_LINE_SHIFT in riscv.mk
Define platform specific maximum cache line size in address lines.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Je
riscv: core: define CFG_MAX_CACHE_LINE_SHIFT in riscv.mk
Define platform specific maximum cache line size in address lines.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f1badf16 | 17-Nov-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: include: cache_helpers.h: allow reusing architecture-dependent code
To allow reuse of architecture-dependent code, divide original cache_helpers.h into two separate header files core/$arch/inc
core: include: cache_helpers.h: allow reusing architecture-dependent code
To allow reuse of architecture-dependent code, divide original cache_helpers.h into two separate header files core/$arch/include/kernel/cache_helpers_arch.h and core/include/kernel/cache_helpers.h
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> [jf: set author to be same as Signed-off-by:] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| b2c54937 | 24-Oct-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: include: kernel: add tee_l2cc_mutex.h
The tee_l2cc_mutex.h header file is required by core/mm/core_mmu.c and core/mm/vm.c, therefore, add an empty one to pass compilation.
Signed-off-by: Mar
riscv: include: kernel: add tee_l2cc_mutex.h
The tee_l2cc_mutex.h header file is required by core/mm/core_mmu.c and core/mm/vm.c, therefore, add an empty one to pass compilation.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 8fe58e85 | 24-Oct-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: include: add misc_arch.h
Nothing to define for now.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| 4e9ed1a9 | 17-Nov-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: include: misc.h: divide into misc.h and misc_arch.h
get_core_pos() is architecture-independent function and could be re-used by an arch implementation, therefore, move it to a separate header
core: include: misc.h: divide into misc.h and misc_arch.h
get_core_pos() is architecture-independent function and could be re-used by an arch implementation, therefore, move it to a separate header file core/include/kernel/misc.h, and, keep architecture-dependent code in core/$arch/include/kernel/misc_arch.h
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> [jf: set author to be same as Signed-off-by:] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 2d7720f1 | 11-Nov-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add fault mitigations in ree_fs_ta_open()
Adds and enables fault mitigation in ree_fs_ta_open() to check the signature of the TA before returning success.
Acked-by: Jerome Forissier <jerome.f
core: add fault mitigations in ree_fs_ta_open()
Adds and enables fault mitigation in ree_fs_ta_open() to check the signature of the TA before returning success.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c8219657 | 01-Apr-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add fault mitigations in buf_ta_open()
Adds and enables fault mitigation in buf_ta_open() to check both the signature of the TA and then also the hash of the TA before returning success.
Acke
core: add fault mitigations in buf_ta_open()
Adds and enables fault mitigation in buf_ta_open() to check both the signature of the TA and then also the hash of the TA before returning success.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 8a697013 | 01-Apr-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add fault mitigations to shdr_verify_signature*()
Adds fault mitigations to shdr_verify_signature() and shdr_verify_signature2(). shdr_verify_signature() and shdr_verify_signature2() are calle
core: add fault mitigations to shdr_verify_signature*()
Adds fault mitigations to shdr_verify_signature() and shdr_verify_signature2(). shdr_verify_signature() and shdr_verify_signature2() are called using the wrapper FTMN_CALL_FUNC() which verifies that the correct function was called and that the return value hasn't been tampered with.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b303be92 | 01-Apr-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
drivers: crypto: add stubbed fault mitigation in crypto_acipher_rsassa_verify()
Adds a stubbed fault mitigation for the drivers version of crypto_acipher_rsassa_verify). End the function with FTMN_C
drivers: crypto: add stubbed fault mitigation in crypto_acipher_rsassa_verify()
Adds a stubbed fault mitigation for the drivers version of crypto_acipher_rsassa_verify). End the function with FTMN_CALLEE_DONE() to record that the function was indeed called and a redundant copy of the return value.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 8f6ac972 | 01-Apr-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ltc: add fault mitigation in crypto_acipher_rsassa_verify()
Adds fault mitigations in crypto_acipher_rsassa_verify() and dependent functions in libTomCrypt in order to include the critical fin
core: ltc: add fault mitigation in crypto_acipher_rsassa_verify()
Adds fault mitigations in crypto_acipher_rsassa_verify() and dependent functions in libTomCrypt in order to include the critical final memcompare.
This fault mitigation is only enabled with the calling function enabled fault mitigations and CFG_CORE_FAULT_MITIGATION is 'y'.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 3227a4c6 | 01-Apr-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add fault mitigation tests
Adds some simple test for the fault mitigation routines.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@lina
core: add fault mitigation tests
Adds some simple test for the fault mitigation routines.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7e75ca54 | 01-Apr-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
Basic fault mitigation routines
Adds basic fault mitigation routines designed to help protecting from fault injection attacks on the hardware. This is by no means bullet proof, but it should at leas
Basic fault mitigation routines
Adds basic fault mitigation routines designed to help protecting from fault injection attacks on the hardware. This is by no means bullet proof, but it should at least improve the situation.
These routines focus on verifying that a function has been called and that the returned value matches the result from the function. This is done by having a handshake between the caller and the callee where also the return value is transmitted in a separate channel.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 593b94ee | 23-Nov-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ffa: remove pager annotations
Configuration with pager and FF-A is currently not supported. Supporting this would require extensions to the FF-A specification to be able to load OP-TEE with pa
core: ffa: remove pager annotations
Configuration with pager and FF-A is currently not supported. Supporting this would require extensions to the FF-A specification to be able to load OP-TEE with paging enabled. So far we don't have any platforms with FF-A which are memory constrained enough that paging can be motivated. If this would change we'll have a good use case to test with when adding pager support for FF-A.
Currently we have a few pager annotations (DECLARE_KEEP_PAGER() and __*_unpaged) which are effectively unused. So save us from adding yet more unused annotations by removing the few we have in the FF-A specific code.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| a951fe52 | 16-Nov-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: arm: stmm: use mempool to decompress stmm image
Changes StMM management to have zlib using default mempool to allocate buffers for StMM image decompression. This is useful as the process can r
core: arm: stmm: use mempool to decompress stmm image
Changes StMM management to have zlib using default mempool to allocate buffers for StMM image decompression. This is useful as the process can require buffer of several kilobytes.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 27c1358c | 18-Nov-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: arm: stmm: preserve usr_lr register in stmm context
Adds management of CPU user mode LR register when executing StMM.
Generic function __thread_enter_user_mode() does not load that register i
core: arm: stmm: preserve usr_lr register in stmm context
Adds management of CPU user mode LR register when executing StMM.
Generic function __thread_enter_user_mode() does not load that register in the user mode context while StMM expects it is preserved between exit and next entry. Therefore this change loads and saves that register into StMM context from stmm_enter_user_mode() while in thread entry atomic context.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| cc4054ff | 17-Nov-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: arm: thread: 32bit helpers thread_get_usr_lr()/thread_set_usr_lr()
Adds helper function thread_get_usr_lr() and thread_set_usr_lr() to read and write CPU USR_LR banked register.
Reviewed-by:
core: arm: thread: 32bit helpers thread_get_usr_lr()/thread_set_usr_lr()
Adds helper function thread_get_usr_lr() and thread_set_usr_lr() to read and write CPU USR_LR banked register.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| fc5444d8 | 16-Nov-2022 |
Ding Tao <miyatsu@qq.com> |
core: include: Fix simple typo in drivers/stm32_gpio.h
Replace "Configuratioh" with "Configuration".
Signed-off-by: Ding Tao <miyatsu@qq.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.
core: include: Fix simple typo in drivers/stm32_gpio.h
Replace "Configuratioh" with "Configuration".
Signed-off-by: Ding Tao <miyatsu@qq.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 438f0055 | 17-Oct-2022 |
Jelle Sels <jelle.sels@arm.com> |
core: ffa: Add support for FFA_MEM_PERM_GET/SET
Handle FFA_MEM_PERM_GET and FFA_MEM_PERM_SET interfaces for enabling SPs to query and set the access rights of their memory regions. These interfaces
core: ffa: Add support for FFA_MEM_PERM_GET/SET
Handle FFA_MEM_PERM_GET and FFA_MEM_PERM_SET interfaces for enabling SPs to query and set the access rights of their memory regions. These interfaces are only permitted in the initialization phase thus a new state variable is being introduced in sp_session. SPs indicate the end of their initialization phase through the FFA_MSG_WAIT interface.
Co-developed-by: Imre Kis <imre.kis@arm.com> Signed-off-by: Imre Kis <imre.kis@arm.com> Signed-off-by: Jelle Sels <jelle.sels@arm.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| cb94c145 | 21-Oct-2022 |
Weizhao Jiang <weizhaoj@amazon.com> |
core: implement a method to dump user TA runtime status
This patch is to dump user TA runtime status for debug purposes. The change includes: 1. Add new command (STATS_CMD_TA_STATS) in the stats PTA
core: implement a method to dump user TA runtime status
This patch is to dump user TA runtime status for debug purposes. The change includes: 1. Add new command (STATS_CMD_TA_STATS) in the stats PTA. 2. Add tee_ta_dump_stats() to scan all ongoing TA instance and sessions and snapshot their status. 3. Add new function: entry_dump_memstats() to __utee_entry() to get TA heap statistics. 4. Add new compile option (CFG_TA_STATS, default n) to enable this feature.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Tested-by: Weizhao Jiang <weizhaoj@amazon.com> Signed-off-by: Weizhao Jiang <weizhaoj@amazon.com> [jf: edit commit message] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| dc23c448 | 20-Oct-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: versal: authentication driver
This driver uses the PLM xilsecure service to deliver authentication functionality using AES-GCM.
The driver currently does not handle unaligned data and lengt
crypto: versal: authentication driver
This driver uses the PLM xilsecure service to deliver authentication functionality using AES-GCM.
The driver currently does not handle unaligned data and lengths; due to this the corresponding xtest regression test will not pass (xtest -t regression 4005 will fail).
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 614bc034 | 04-Jul-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: versal: interprocessor communication
Interface to the PLM xilsecure service.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
crypto: versal: interprocessor communication
Interface to the PLM xilsecure service.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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