| 0adca93a | 04-Jan-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
core: dt_driver: differentiate error codes if property is not found
Differentiates error codes in dt_driver_device_from_node_idx_prop() if the requested resource is not found by returning TEE_ERROR_
core: dt_driver: differentiate error codes if property is not found
Differentiates error codes in dt_driver_device_from_node_idx_prop() if the requested resource is not found by returning TEE_ERROR_ITEM_NOT_FOUND. This is useful to differentiate cases for optional properties in drivers.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 0aed2b11 | 25-Feb-2021 |
Vincent Guittot <vincent.guittot@linaro.org> |
plat-vexpress: fvp and qemuv8a support building with CFG_SCMI_SCPFW=y
Adds support for CFG_SCMI_SCPFW to platform flavors vexpress-fvp and vexpress-qemuv8a. Both rely on the same SCP-firmware so-cal
plat-vexpress: fvp and qemuv8a support building with CFG_SCMI_SCPFW=y
Adds support for CFG_SCMI_SCPFW to platform flavors vexpress-fvp and vexpress-qemuv8a. Both rely on the same SCP-firmware so-called product configuration named "optee-fvp".
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 986fccc8 | 30-Jun-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm32mp1: support building with CFG_SCMI_SCPFW=y
Support building with CFG_SCMI_SCPFW=y. This configuration embeds SCMI services built from SCP-firmware implementation instead of the scmi-msg d
plat-stm32mp1: support building with CFG_SCMI_SCPFW=y
Support building with CFG_SCMI_SCPFW=y. This configuration embeds SCMI services built from SCP-firmware implementation instead of the scmi-msg drivers and platform local scmi_server.c.
This change also default disables SCMI SiP SMC entries as the PTA is the default SCMI commands entry point and ensures at least one of the SCMI server implementation is default enabled, that is, if CFG_SCMI_SCPFW is disabled then CFG_SCMI_MSG_DRIVERS is default enabled.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 7ff45442 | 02-Dec-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: pta: scmi: support SCP-firmware SCMI resources
Updates SCMI PTA to use SCP-firmware resources when CFG_SCMI_SCPFW=y.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Fori
core: pta: scmi: support SCP-firmware SCMI resources
Updates SCMI PTA to use SCP-firmware resources when CFG_SCMI_SCPFW=y.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 4c4212e9 | 25-Feb-2021 |
Vincent Guittot <vincent.guittot@linaro.org> |
core: lib: scmi-server: Build a SCMI server from SCP-firmware
Adds build of an SCMI server library using SCP-firmware source tree upon boolean configuration switch CFG_SCMI_SCPFW. Platform must set
core: lib: scmi-server: Build a SCMI server from SCP-firmware
Adds build of an SCMI server library using SCP-firmware source tree upon boolean configuration switch CFG_SCMI_SCPFW. Platform must set the SCP firmware target product with CFG_SCMI_SCPFW_PRODUCT and the root path of the SCP-firmware source tree with CFG_SCP_FIRMWARE.
CFG_SCMI_SCPFW and CFG_SCMI_MSG_DRIVERS are exclusives alternate implementations of SCMI services. The former implements almost all the SCMI specification while the later implements only basic SCMI services.
SCP-firmware is configured with CMake as an external project to generate the embedded module resource source and header files to be built with SCP-firmware.
This commit integrates the 2 SCP-firmware products designed for OP-TEE in SCP-firmware source tree. Product optee-fvp targets platform vexpress flavors FVP and Qemus. Product optee-stm32mp1 targets platform stm32mp1.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8b7eff36 | 17-Jun-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: pta: scmi: simplify scmi-msg case in open session
Allows session opening when CFG_SCMI_MSG_DRIVERS is enabled instead of testing the 2 possible scmi-msg transport protocol config switches.
Ac
core: pta: scmi: simplify scmi-msg case in open session
Allows session opening when CFG_SCMI_MSG_DRIVERS is enabled instead of testing the 2 possible scmi-msg transport protocol config switches.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 16a5030f | 02-Dec-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: pta: scmi: internal switches for supported transports
Adds internal configuration switch _CFG_SMCI_PTA_SMT_HEADER and _CFG_SCMI_PTA_MSG_HEADER to specify which are supported. This change will
core: pta: scmi: internal switches for supported transports
Adds internal configuration switch _CFG_SMCI_PTA_SMT_HEADER and _CFG_SCMI_PTA_MSG_HEADER to specify which are supported. This change will ease integration of the alternate SCMI server build from SCP-firmware.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| b836852d | 08-Dec-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: use IS_ENABLED2()
Replaces use of IS_ENABLED() with IS_ENABLED2() where applicable.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@
core: use IS_ENABLED2()
Replaces use of IS_ENABLED() with IS_ENABLED2() where applicable.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 5df61a5d | 05-Jul-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: clk: add support for clk_get_rates_array
In order to query rates from clients, add get_rates_array() which returns a supported rate array.
Reviewed-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
drivers: clk: add support for clk_get_rates_array
In order to query rates from clients, add get_rates_array() which returns a supported rate array.
Reviewed-by: Xiaoxu Zeng <zengxiaoxu@huawei.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Clément Léger <clement.leger@bootlin.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 10fb0d97 | 12-Dec-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_bsec: use DT NVMEM layout API
Uses OTP definition in the device tree, by using the function stm32_bsec_find_otp_in_nvmem_layout() and removes the hardcoded OTP index in platform confi
drivers: stm32_bsec: use DT NVMEM layout API
Uses OTP definition in the device tree, by using the function stm32_bsec_find_otp_in_nvmem_layout() and removes the hardcoded OTP index in platform config.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 474ad185 | 06-Jan-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp1: conf: mandate the use of device tree on STM32MP1x platforms
STM32MP1x platforms now mandate an embedded device tree using CFG_EMBED_DTB_SOURCE_FILE. This decision simplifies platform
plat-stm32mp1: conf: mandate the use of device tree on STM32MP1x platforms
STM32MP1x platforms now mandate an embedded device tree using CFG_EMBED_DTB_SOURCE_FILE. This decision simplifies platform configuration and complies with existing flavors that all define an embedded DT. This change makes stm32mp157c-dk2.dts the default embedded DTB when none is set.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 0ec45216 | 12-Dec-2022 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_bsec: st,non-secure-otp-provisioning property
Implementation of a new "st,non-secure-provisioning-otp" property, destined for non-secure OTP access with restrictions. At BSEC initiali
drivers: stm32_bsec: st,non-secure-otp-provisioning property
Implementation of a new "st,non-secure-provisioning-otp" property, destined for non-secure OTP access with restrictions. At BSEC initialization, OTPs defined with this property will grant their access to non-secure world only if the fuses are not permanently locked.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 7cb0cbba | 06-Jan-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32mp15_huk: fix use of stm32mp_is_closed_device()
This function is no more defined because it was superseded by BSEC driver API function stm32_bsec_get_state().
Implements use of the ne
drivers: stm32mp15_huk: fix use of stm32mp_is_closed_device()
This function is no more defined because it was superseded by BSEC driver API function stm32_bsec_get_state().
Implements use of the new API.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 683b6d2c | 03-Jan-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: kernel: move otp_stubs.c to core/kernel
otp_stubs.c is architecture-agnostic, therefore, move it from core/arch/arm/kernel to core/kernel.
Signed-off-by: Marouene Boubakri <marouene.boubakri@
core: kernel: move otp_stubs.c to core/kernel
otp_stubs.c is architecture-agnostic, therefore, move it from core/arch/arm/kernel to core/kernel.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| d1c0af7d | 30-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv.mk: disable unsupported configuration flags
Features which are not supported, or, specific to other architectures are disabled.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.c
core: riscv.mk: disable unsupported configuration flags
Features which are not supported, or, specific to other architectures are disabled.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| e2f6d2fb | 30-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: add plat-virt
Add Qemu Virt RISC-V platform. Reference: https://www.qemu.org/docs/master/system/riscv/virt.html
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: J
core: riscv: add plat-virt
Add Qemu Virt RISC-V platform. Reference: https://www.qemu.org/docs/master/system/riscv/virt.html
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 8d6c1b18 | 05-Jan-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm32mp1: restore BSEC SIP services on STM32MP15
U-Boot and Linux kernel use BSEC OP-TEE services on STM32MP15 but do not yet integrate BSEC PTA drivers for OTP accesses and still rely on OP-TE
plat-stm32mp1: restore BSEC SIP services on STM32MP15
U-Boot and Linux kernel use BSEC OP-TEE services on STM32MP15 but do not yet integrate BSEC PTA drivers for OTP accesses and still rely on OP-TEE BSEC SMC SiP service. Therefore restore the service for STM32MP15 platform flavors. The service will be default disabled once U-Boot and Linux kernel are ready.
Fixes: eab9487631cc ("plat-stm32mp1: deprecate BSEC SIP services") Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 0042538e | 05-Jan-2023 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm32mp1: fix visibility of stm32_bsec_shadow_register()
Makes stm32_bsec_shadow_register() function a visible driver API function as it is needed when CFG_STM32_BSEC_SIP is enabled. Fixed comm
plat-stm32mp1: fix visibility of stm32_bsec_shadow_register()
Makes stm32_bsec_shadow_register() function a visible driver API function as it is needed when CFG_STM32_BSEC_SIP is enabled. Fixed commit made it a local function which was wrong.
Fixes: a638030bce84 ("drivers: stm32_bsec: remove unused functions") Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| b7c495e0 | 01-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: provide delay_arch.h
Implement timeout_init_us() and timeout_elapsed().
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@lin
core: riscv: provide delay_arch.h
Implement timeout_init_us() and timeout_elapsed().
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c67c4c8d | 01-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: kernel: delay: sort-out architecture-independant code from arch dir
This commit moves core/arch/arm/kernel/delay.c to core/kernel/delay.c. Keeps architecture-dependant code in core/arch/$ARCH/
core: kernel: delay: sort-out architecture-independant code from arch dir
This commit moves core/arch/arm/kernel/delay.c to core/kernel/delay.c. Keeps architecture-dependant code in core/arch/$ARCH/include/kernel/delay_arch.h and moves generic functions to core/include/kernel/delay.h
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 6454758b | 01-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: add time source based on time registers
Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode and CLINT MTIME register for M-Mode. CFG_RISCV_TIME_SOURCE_RDTIME flag to
core: riscv: add time source based on time registers
Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode and CLINT MTIME register for M-Mode. CFG_RISCV_TIME_SOURCE_RDTIME flag to enable or not building the time source. CFG_RISCV_MTIME_RATE defines the timer rate, default to 10MHz.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 14c0df4e | 01-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: move tee_time.c and tee_time_ree.c to core/kernel
tee_time.c and tee_time_ree.c are architecture-independant code therefore move them from core/arch/arm/kernel to core/kernel.
Signed-off-by:
core: move tee_time.c and tee_time_ree.c to core/kernel
tee_time.c and tee_time_ree.c are architecture-independant code therefore move them from core/arch/arm/kernel to core/kernel.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d26e3419 | 01-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: provide <kernel/time.h>
Add read_time() function to get time based on CSR_TIME and CSR_HTIME registers for S-Mode and CLINT MTIME register for M-Mode.
Signed-off-by: Marouene Boubakri
core: riscv: provide <kernel/time.h>
Add read_time() function to get time based on CSR_TIME and CSR_HTIME registers for S-Mode and CLINT MTIME register for M-Mode.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 380907c9 | 01-Dec-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
core: riscv: implement core local interruptor (clint) driver
An initial implementation of RISC-V CLINT driver with MTIMER device to provide machine-level timer functionality.
Signed-off-by: Marouen
core: riscv: implement core local interruptor (clint) driver
An initial implementation of RISC-V CLINT driver with MTIMER device to provide machine-level timer functionality.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 664463b3 | 27-Dec-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: use SM3 crypto accelerated function
Uses the recently provided accelerated SM3 function in the SM3 implementation.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens
core: use SM3 crypto accelerated function
Uses the recently provided accelerated SM3 function in the SM3 implementation.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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