plat-stm32mp1: scmi_server: default use OP-TEE shared memory

Adds configuration switch CFG_STM32MP1_SCMI_SHM_SYSRAM that is default
disabled. When disabled, CFG_STM32MP1_SCMI_SHM_BASE defaults to 0

plat-stm32mp1: scmi_server: default use OP-TEE shared memory

Adds configuration switch CFG_STM32MP1_SCMI_SHM_SYSRAM that is default
disabled. When disabled, CFG_STM32MP1_SCMI_SHM_BASE defaults to 0
which means OP-TEE SMCI server uses OP-TEE native shared memory
registered by clients. When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled
CFG_STM32MP1_SCMI_SHM_BASE is force the base address of the SYRAM
last 4KByte page.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: scmi_server: support use of OP-TEE shared memory

Updates scmi_server configuration and implementation for the platform
to use OP-TEE native shared memory instead of device memory mapp

plat-stm32mp1: scmi_server: support use of OP-TEE shared memory

Updates scmi_server configuration and implementation for the platform
to use OP-TEE native shared memory instead of device memory mapped
SRAM for SCMI messages transfer. With this change, configuring
CFG_STM32MP1_SCMI_SHM_BASE to 0 allows such setup.

This change moves registration of CFG_STM32MP1_SCMI_SHM_BASE as
non-secure mapped device memory from main.c to scmi_server.c
to have all SCMI related platform resources defined from that
source file.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: core controller uses irq_chip list head

Changes core interrupt controller API function (from interrupt.c) to
use the handlers list head added in struct itr_handler instead of
local

core: interrupt: core controller uses irq_chip list head

Changes core interrupt controller API function (from interrupt.c) to
use the handlers list head added in struct itr_handler instead of
local list head. With this change, main itr_chip is managed as a
standard itr_chip and its interrupts can be fetched from the irq_chip
handler functions.

CPU primary interrupt handler itr_handle() function now calls
generic interrupt controller interrupt_call_handlers().

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: hfic: implement mask/unmask handlers

Implements Hafnium interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers. This change is needed as
mask/unmask ope

drivers: hfic: implement mask/unmask handlers

Implements Hafnium interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers. This change is needed as
mask/unmask operation handlers are required by the new native interrupt
framework.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: atmel_saic: implement mask/unmask handlers

Implements Atmel SAIC interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers. This change is needed as
mask/u

drivers: atmel_saic: implement mask/unmask handlers

Implements Atmel SAIC interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers. This change is needed as
mask/unmask operation handlers are required by the new native interrupt
framework.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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driver: gic: implement mask/unmask handler

Implements GIC interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers.

Reviewed-by: Jens Wiklander <jens.wiklander@li

driver: gic: implement mask/unmask handler

Implements GIC interrupts mask/unmask operation handlers using
interrupt disable/enable operation handlers.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: interrupt: interrupt chip framework

Extends itr_chip framework to allow interrupt controllers to register
as interrupt chip and other interrupt management methods it their
owns interrupt consu

core: interrupt: interrupt chip framework

Extends itr_chip framework to allow interrupt controllers to register
as interrupt chip and other interrupt management methods it their
owns interrupt consumer through the interrupt_xxx() API function.

This change does not modify the existing interrupt API function that
allow a driver to get an interrupt from the CPU main interrupt controller.
A later change will remove these old API functions.

This changes adds fields in existing structures defined in interrupt.h:
- itr_handler::chip back references the interrupt controller
- itr_chip::handlers is a list head for controller registered handlers
- itr_chip::name for debug trace purpose
- itr_ops::mask and itr_ops::unmask to mask/unmask an interrupt

The new API functions exposed to interrupt consumers are:
- interrupt_add_configure_handler(), interrupt_remove_handler() and
helper functions interrupt_add_handler() and
interrupt_add_handler_with_chip();
- interrupt_alloc_add_handler() and interrupt_remove_free_handler();
- interrupt_configure(), interrupt_enable(), interrupt_disable(),
interrupt_mask() and interrupt_unmask();

Interrupt controllers shall call generic API function
interrupt_call_handlers() to have their registered consumer handlers
called upon their related interrupt occurrences.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: add missing braces in IO compensation function

Adds missing braces in stm32mp_syscfg_enable_io_compensation().

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gati

plat-stm32mp1: add missing braces in IO compensation function

Adds missing braces in stm32mp_syscfg_enable_io_compensation().

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: fix timeout initializations

Fixes timeout initialization to ensure timeout monitoring starts
only once PWR regulator is enabled in stm32mp1_pwr driver and
once IO compensation is enab

plat-stm32mp1: fix timeout initializations

Fixes timeout initialization to ensure timeout monitoring starts
only once PWR regulator is enabled in stm32mp1_pwr driver and
once IO compensation is enabled in stm32mp1_syscfg driver.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: drivers: stm32_bsec: Fix conflicting types due to enum/integer mismatch

This is an error with gcc13 [-Werror=enum-int-mismatch]

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-

core: drivers: stm32_bsec: Fix conflicting types due to enum/integer mismatch

This is an error with gcc13 [-Werror=enum-int-mismatch]

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jose Quaresma <jose.quaresma@foundries.io>

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core: mm: Fix conflicting types due to enum/integer mismatch

This is an error with gcc13 [-Werror=enum-int-mismatch]

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jose Quar

core: mm: Fix conflicting types due to enum/integer mismatch

This is an error with gcc13 [-Werror=enum-int-mismatch]

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jose Quaresma <jose.quaresma@foundries.io>

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core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename

core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename "mva" to common terminology, such as "va". This PR renames "mva"
to "va" in TLB operations for ARM64 and RISC-V. For ARM32, "mva" is
reserved because it is really defined in ARM32's documentations.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: pinctrl: fix line breaks in propotypes

Fixes pin ctrl.h header file prototype declaration as per preferred
by toolchains as clang.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Sign

drivers: pinctrl: fix line breaks in propotypes

Fixes pin ctrl.h header file prototype declaration as per preferred
by toolchains as clang.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: dt_driver: swap TEE_result and retrieved device reference

Changes dt_driver callback function to return a TEE_Result value
and pass retrieved device reference by a output argument rather
than

core: dt_driver: swap TEE_result and retrieved device reference

Changes dt_driver callback function to return a TEE_Result value
and pass retrieved device reference by a output argument rather
than the opposite.

This change updates dt_driver.c, dt_driver.h and all drivers
implementing related dt_driver callback function.

As a consequence, this change removes all type definition related
to device specific callback handler function types which are useless
as all these now comply with type dt_driver_probe_func defined in
dt_driver.h.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: Introduce next_level field of struct core_mmu_table_info

The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-g

core: mm: Introduce next_level field of struct core_mmu_table_info

The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-grained table,
while RISC-V adopts decreasing style. Therefore, we add a "next_level"
field into the struct core_mmu_table_info, which represents the next
finer-grained translation level. By doing this, we can decouple the
core address translation rule from architecture specific manner.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: Introduce core_mmu_level_in_range()

Since the checking of the valid translation level is architecture
specific, the core_mmu_level_in_range() is introduced and every
architecture could imp

core: mm: Introduce core_mmu_level_in_range()

Since the checking of the valid translation level is architecture
specific, the core_mmu_level_in_range() is introduced and every
architecture could implement the function with their own translation
rules.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: Reduce size of struct core_mmu_table_info

The level and shift of struct core_mmu_table_info could be uint8_t to
reduce the size of the structure.

Signed-off-by: Alvin Chang <alvinga@andes

core: mm: Reduce size of struct core_mmu_table_info

The level and shift of struct core_mmu_table_info could be uint8_t to
reduce the size of the structure.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Fix misuse of cppflags

The -mxxx and -Wxxx are not preprocessor flags. Fix it by defining them
as C flags.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Foriss

core: riscv: Fix misuse of cppflags

The -mxxx and -Wxxx are not preprocessor flags. Fix it by defining them
as C flags.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: sp: implement FF-A v1.1 boot protocol

Implement passing the boot info to Secure Partitions in the new format
defined by FF-A v1.1. The change is backwards compatible by keeping the
already exi

core: sp: implement FF-A v1.1 boot protocol

Implement passing the boot info to Secure Partitions in the new format
defined by FF-A v1.1. The change is backwards compatible by keeping the
already existing FF-A v1.0 format too. Which format to use is decided
based on the "ffa-version" field in the SP's manifest. The register to
use for passing the boot info blob's address is based on the
"gp-register-num" field.

Link: https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html#partition-properties
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: sp: fix session handling in sp_first_run

Currently the error handling after sp_enter() calls vm_unmap() without
activating the correct session with ts_push_current_session(), fix this.
Also fi

core: sp: fix session handling in sp_first_run

Currently the error handling after sp_enter() calls vm_unmap() without
activating the correct session with ts_push_current_session(), fix this.
Also fix the returned error code to use TEE_* instead of FFA_*.

Fixes: 6d618ba1d612 ("core: sp: map device regions from SP manifest")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: sp: fix unmap in sp_first_run

Fix the usage of vm_unmap() in sp_first_run. The functions expects the
memory size as the last argument, but currently the number of pages is
passed instead.

Fix

core: sp: fix unmap in sp_first_run

Fix the usage of vm_unmap() in sp_first_run. The functions expects the
memory size as the last argument, but currently the number of pages is
passed instead.

Fixes: 7e8d05e4c35d ("core: sp: Pass manifest fdt to SP")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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drivers: gic: prevent accessing unimplemented GIC registers

The GIC method for probing for the highest implemented interrupt ignored
is done by writing & reading to GIC registers GICD_ISENABLER<n> &

drivers: gic: prevent accessing unimplemented GIC registers

The GIC method for probing for the highest implemented interrupt ignored
is done by writing & reading to GIC registers GICD_ISENABLER<n> &
GICD_ICENABLER<n> that are not always implemented. This causes an
error indication in GIC register GICT_ERR0_STATUS. To prevent this,
Check in GIC register GICD_TYPER how many SPI blocks are implemented
and access only implemented registers.

Signed-off-by: Izhar Nevo <inevo@amazon.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: dt_driver: add helper for old fashion interrupt bindings

Adds a helper function dt_driver_device_from_node_idx_prop_phandle()
in device tree driver probing framework for when a DT node propert

core: dt_driver: add helper for old fashion interrupt bindings

Adds a helper function dt_driver_device_from_node_idx_prop_phandle()
in device tree driver probing framework for when a DT node property
contains a resource references but not the related device phandle as
first property cell, as for property "interrupts" which should get the
interrupt controller phandle from property "interrupt-parent". This
change aims at supporting "interrupts" property DT bindings.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver: define interrupt controller drivers identifier

Defines identifier DT_DRIVER_INTERRUPT in dt_driver_type enumerated type
for interrupt controller drivers.

Acked-by: Jens Wiklander <

core: dt_driver: define interrupt controller drivers identifier

Defines identifier DT_DRIVER_INTERRUPT in dt_driver_type enumerated type
for interrupt controller drivers.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: fix default setting GPIO as non-secure

Fixes STM32MP13 sequence that default configures GPIO as non-secure
from set_all_gpios_non_secure() registered at early_init_late initcall
level

plat-stm32mp1: fix default setting GPIO as non-secure

Fixes STM32MP13 sequence that default configures GPIO as non-secure
from set_all_gpios_non_secure() registered at early_init_late initcall
level, that is at same level driver are initially probed by dt_driver
framework. This result on set_all_gpios_non_secure() possibly needing
a bank resource before it is probed. Fix that by removing initcall
function set_all_gpios_non_secure() and default configuring GPIO pins
for STM32MP13 variant on their GPIO bank registering.

Fixes: 077d486ef09d ("drivers: stm32_gpio: add helper function stm32_gpio_get_bank()")
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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