crypto: rename struct x25519_keypair

Since X25519 and X448 have the same key pair structure,
so we rename struct x25519_keypair as struct montgomery_keypair.

Signed-off-by: loubaihui <loubaihui1@hu

crypto: rename struct x25519_keypair

Since X25519 and X448 have the same key pair structure,
so we rename struct x25519_keypair as struct montgomery_keypair.

Signed-off-by: loubaihui <loubaihui1@huawei.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-o

core: arm: Rename primary_init_intc() to boot_primary_init_intc()

Since interrupt controllers are usually initialized in boot stage,
rename primary_init_intc() to boot_primary_init_intc().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()

main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by rena

core: arm: Rename main_secondary_init_intc() to boot_secondary_init_intc()

main_secondary_*() is an ambiguous name since it conveys no meaning
relative to the purpose of the function. Fix it by renameing to
boot_secondary_init_intc(), since interrupt controllers are always
initialized in boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: stm32_gpio: move definitions to source file

Moves macros and structures definitions from stm32_gpio.h header file
to the driver source file as these definition do not need to be
visible fro

drivers: stm32_gpio: move definitions to source file

Moves macros and structures definitions from stm32_gpio.h header file
to the driver source file as these definition do not need to be
visible from other drivers thank to pin control abstraction.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_i2c: remove cases when CFG_DRIVERS_PINCTRL is disabled

Removes implementation when CFG_DRIVERS_PINCTRL is disables as stm32mp1
platform configuration enforces the switch is enabled.

drivers: stm32_i2c: remove cases when CFG_DRIVERS_PINCTRL is disabled

Removes implementation when CFG_DRIVERS_PINCTRL is disables as stm32mp1
platform configuration enforces the switch is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_uart: remove cases when CFG_DRIVERS_PINCTRL is disabled

Removes implementation when CFG_DRIVERS_PINCTRL is disables as stm32mp1
platform configuration enforces the switch is enabled.

drivers: stm32_uart: remove cases when CFG_DRIVERS_PINCTRL is disabled

Removes implementation when CFG_DRIVERS_PINCTRL is disables as stm32mp1
platform configuration enforces the switch is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: remove cases when CFG_DRIVERS_PINCTRL is disabled

Removes implementation when CFG_DRIVERS_PINCTRL is disables as stm32mp1
platform configuration enforces the switch is enabled.

drivers: stm32_gpio: remove cases when CFG_DRIVERS_PINCTRL is disabled

Removes implementation when CFG_DRIVERS_PINCTRL is disables as stm32mp1
platform configuration enforces the switch is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: enable CFG_DRIVERS_PINCTRL

Changes platform stm32mp1 configuration to always enable
CFG_DRIVERS_PINCTRL. The platform requires pinctrl_apply_state() to
be unpaged has it can be

plat-stm32mp1: conf: enable CFG_DRIVERS_PINCTRL

Changes platform stm32mp1 configuration to always enable
CFG_DRIVERS_PINCTRL. The platform requires pinctrl_apply_state() to
be unpaged has it can be used during PM suspend and resume sequences.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL

Updates stm32_i2c driver for when CFG_DRIVERS_PINCTRL is enabled making
I2C driver to get pin control configuration using the generic pin
control fram

drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL

Updates stm32_i2c driver for when CFG_DRIVERS_PINCTRL is enabled making
I2C driver to get pin control configuration using the generic pin
control framework. When enabled, stm32_i2c driver get the active and
sleep pin control configuration from the device tree. Sleep pinctrl
configuration is optional.

SE050 and STM32MP1 PMIC drivers that use the stm32_i2c bus are both
updated accordingly.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_uart: support CFG_DRIVERS_PINCTRL

Updates stm32_uart driver for when CFG_DRIVERS_PINCTRL is enabled making
UART driver to get pin control configuration using the generic pin
control f

drivers: stm32_uart: support CFG_DRIVERS_PINCTRL

Updates stm32_uart driver for when CFG_DRIVERS_PINCTRL is enabled making
UART driver to get pin control configuration using the generic pin
control framework.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: shared_resources: support CFG_DRIVERS_PINCTRL

Adds shared resources helper functions stm32mp_register_secure_pinctrl()
and stm32mp_register_non_secure_pinctrl() for when a platform dr

plat-stm32mp1: shared_resources: support CFG_DRIVERS_PINCTRL

Adds shared resources helper functions stm32mp_register_secure_pinctrl()
and stm32mp_register_non_secure_pinctrl() for when a platform driver
registers pins from a pin control state with secure or non-secure
attribute. These function are required when CFG_DRIVERS_PINCTRL is
enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: add helper function stm32_pinctrl_set_secure_cfg()

Adds helper function stm32_pinctrl_set_secure_cfg() to set the
GPIO pin secure state (secure or non-secure) for each pin refer

drivers: stm32_gpio: add helper function stm32_pinctrl_set_secure_cfg()

Adds helper function stm32_pinctrl_set_secure_cfg() to set the
GPIO pin secure state (secure or non-secure) for each pin referenced
by a pin control state.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: add helper function stm32_gpio_pinctrl_bank_pin()

Adds helper function stm32_gpio_pinctrl_bank_pin() to get an array
of bank and pin IDs related to a pin control state.

Acked-b

drivers: stm32_gpio: add helper function stm32_gpio_pinctrl_bank_pin()

Adds helper function stm32_gpio_pinctrl_bank_pin() to get an array
of bank and pin IDs related to a pin control state.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_gpio: support CFG_DRIVERS_PINCTRL

Changes stm32_gpio driver to support generic pin control framework
(CFG_DRIVERS_PINCTRL=y).

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.c

drivers: stm32_gpio: support CFG_DRIVERS_PINCTRL

Changes stm32_gpio driver to support generic pin control framework
(CFG_DRIVERS_PINCTRL=y).

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: fix size of CMAC update data

In case of an update operation, the total input data size processed
must be a multiple of a block size. The total block size is equal to
the input data si

drivers: caam: fix size of CMAC update data

In case of an update operation, the total input data size processed
must be a multiple of a block size. The total block size is equal to
the input data size and the saved buffer size.

If the reallocation DMA buffer is less than the input data size,
buffer length plus saved buffer size need to be adjusted to align
on multiple of a block size.

Depending on the memory buffer input configuration, the function
caam_dmaobj_sgtbuf_build() might modify the data size to be processed in
the loop.

This case happens sometimes on i.MX platforms where the input buffer
physical address in above 32 bits. This implies reporting the data size
re-ajustment when data is saved in the context buffer.

Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: introduce primary_init_intc() and secondary_init_intc()

Rename interrupt controller initialization functions to
primary_init_intc() and secondary_init_intc(). To be called by
platform b

core: riscv: introduce primary_init_intc() and secondary_init_intc()

Rename interrupt controller initialization functions to
primary_init_intc() and secondary_init_intc(). To be called by
platform boot code to initialize interrupt controller on boot hart
and secondary harts, respectively.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: driver: implement platform-level interrupt controller (PLIC) driver

An initial implementation of RISC-V PLIC driver conforming
to the specification. CFG_RISCV_PLIC flag allows building it
or

riscv: driver: implement platform-level interrupt controller (PLIC) driver

An initial implementation of RISC-V PLIC driver conforming
to the specification. CFG_RISCV_PLIC flag allows building it
or not for platforms with custom PLIC IP.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: rename interrupt controller functions

This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic()

core: rename interrupt controller functions

This commit renames interrupt controller function names
to be more generic:
- Rename main_init_gic() to primary_init_intc()
- Rename secondary_init_gic() to secondary_init_intc()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: mm: initial implementation of memory management routines

An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table l

riscv: mm: initial implementation of memory management routines

An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table levels.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: kernel: asm-defines.c: add defines for struct core_mmu_config

Add CORE_MMU_CONFIG_SIZE and CORE_MMU_CONFIG_SATP defines
to asm-defines.c

Signed-off-by: Marouene Boubakri <marouene.boubakri@n

riscv: kernel: asm-defines.c: add defines for struct core_mmu_config

Add CORE_MMU_CONFIG_SIZE and CORE_MMU_CONFIG_SATP defines
to asm-defines.c

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: mm: core_mmu_arch.h: define translation levels parameters

This commits modify core_mmu_arch.h to:
- Set CORE_MMU_PGDIR_LEVEL to zero, since the deepest translation
level is always zero.
- Set

riscv: mm: core_mmu_arch.h: define translation levels parameters

This commits modify core_mmu_arch.h to:
- Set CORE_MMU_PGDIR_LEVEL to zero, since the deepest translation
level is always zero.
- Set CORE_MMU_BASE_TABLE_LEVEL to (RISCV_PGLEVELS - 1) which the first
translation level depending on the MMU mode.
- Set RISCV_MMU_ASID_WIDTH to number of bits used to represent ASID.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: add dsb_osh()

Implement the use of osh data barrier to ensure that all data
access and modifications have been completed before executing
subsequent instructions.

Signed-off-by: Xiaoxu

core: arm64: add dsb_osh()

Implement the use of osh data barrier to ensure that all data
access and modifications have been completed before executing
subsequent instructions.

Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_bsec: implement the get otp by phandle

Add a new interface stm32_bsec_find_otp_by_phandle() to retrieve
localization of an OTP from a given node phandle.

When the node phandle is abs

drivers: stm32_bsec: implement the get otp by phandle

Add a new interface stm32_bsec_find_otp_by_phandle() to retrieve
localization of an OTP from a given node phandle.

When the node phandle is absent in the NVMEM node, layout_cell->phandle = 0
and reference to this OTP with this API function is not possible.

Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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drivers: stm32_bsec: add support for bits property in the DT

Adds the possibility to specify the number of managed bit in the NVMEM
cell device tree description, using the optional bits property
and

drivers: stm32_bsec: add support for bits property in the DT

Adds the possibility to specify the number of managed bit in the NVMEM
cell device tree description, using the optional bits property
and removes restriction on aligned NVMEM cell on 32-bit word by supporting
bit offset in stm32_bsec_find_otp_in_nvmem_layout().

Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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drivers: stm32_bsec: keep stm32_bsec_permanent_lock_otp() under flag

Keep the function to access the OTP lock under the CFG_STM32_BSEC_WRITE
flag to align with the write function.

Reviewed-by: Etie

drivers: stm32_bsec: keep stm32_bsec_permanent_lock_otp() under flag

Keep the function to access the OTP lock under the CFG_STM32_BSEC_WRITE
flag to align with the write function.

Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>

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