core: notif: remove interrupt assumptions

Removes the assumption in notif_register_driver() that OP-TEE is using
interrupts to notify the normal world. The coming FF-A based
implementation will use

core: notif: remove interrupt assumptions

Removes the assumption in notif_register_driver() that OP-TEE is using
interrupts to notify the normal world. The coming FF-A based
implementation will use FFA_NOTIFICATION_SET for when notifying using an
SPMC at S-EL2 or EL3.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: separate async notification implementation

Separates the implementation of sending asynchronous notifications from
the part managing reception of events. This makes room for an
alternative imp

core: separate async notification implementation

Separates the implementation of sending asynchronous notifications from
the part managing reception of events. This makes room for an
alternative implementation based on FF-A.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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qemu_armv8a: enable testing of notifications using the console

When asynchronous notifications are enabled the console driver in
qemu_armv8a is configured as a top half and bottom half driver allowi

qemu_armv8a: enable testing of notifications using the console

When asynchronous notifications are enabled the console driver in
qemu_armv8a is configured as a top half and bottom half driver allowing
basic testing of the notification framework.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: print regulator tree summary

Changes implementation of regulator_print_state() to better show
the regulator tree hierarchy and renames the function to
regulator_print_tree().

Th

drivers: regulator: print regulator tree summary

Changes implementation of regulator_print_state() to better show
the regulator tree hierarchy and renames the function to
regulator_print_tree().

The function now depends on CFG_DRIVERS_REGULATOR_PRINT_TREE
being enabled.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Co-developed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32mp15: harden RCC secure configuration on ST boards

Enable STM32MP15 RCC secure hardening configuration on ST boards
(DK1, DK2, ED1 and EV1) to assign SoC clocks, reset controllers
and PWR

dts: stm32mp15: harden RCC secure configuration on ST boards

Enable STM32MP15 RCC secure hardening configuration on ST boards
(DK1, DK2, ED1 and EV1) to assign SoC clocks, reset controllers
and PWR regulators to OP-TEE secure world.

This change removes setting of &rcc node status property from
stm32mp157a-dk1.dts, stm32mp157c-dk2.dts as the property is
set from stm32mp15xx-dkx.dtsi that is included from the 2 former
DTS files.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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arm: aspeed: Add cflags for AST2600 SoCs

AST2600 only supports VFPv3-D16, which should be speicifed by cflags
to prevent undef-abort due to unsupoorted instructions generated by
compilers.

Signed-o

arm: aspeed: Add cflags for AST2600 SoCs

AST2600 only supports VFPv3-D16, which should be speicifed by cflags
to prevent undef-abort due to unsupoorted instructions generated by
compilers.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Neal Liu <neal_liu@aspeedtech.com>

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drivers: regulator: fix getting GPIO for level control

Swap the 2 calls to find gpio property in "regulator-gpio" compatible
node. The call that expects to get a TEE_ERROR_ITEM_NOT_FOUND return
valu

drivers: regulator: fix getting GPIO for level control

Swap the 2 calls to find gpio property in "regulator-gpio" compatible
node. The call that expects to get a TEE_ERROR_ITEM_NOT_FOUND return
value (as described in the inline comment) for an unsupported 2nd level
control GPIO can fail with TEE_ERROR_DEFER_DRIVER_INIT return value
when the 1st GPIO phandle listed in the 'gpios' DT node property relates
to a GPIO driver that is not yet probed. Fix that by first getting the
required GPIO control level and then testing presence of other GPIO
phandle in the 'gpios' DT property.

Fixes: f164f0f83420 ("drivers: regulator: GPIO controlled regulator")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: fix warning trace on TZC configuration check

Fix build warning reported by recent toolchains when TZDRAM
memory ends at the UINT32_MAX. This happends for example when
building for the

plat-stm32mp1: fix warning trace on TZC configuration check

Fix build warning reported by recent toolchains when TZDRAM
memory ends at the UINT32_MAX. This happends for example when
building for the stm32mp1-157C_EV1 platform. In such case was GCC
to emit the following warning trace:

core/arch/arm/plat-stm32mp1/plat_tzc400.c: In function ‘init_stm32mp1_tzc’:
core/arch/arm/plat-stm32mp1/plat_tzc400.c:107:61: warning: conversion from ‘uint64_t’ {aka ‘long long unsigned int’} to ‘vaddr_t’ {aka ‘long unsigned int’} changes value from ‘4294967296’ to ‘0’ [-Woverflow]
107 | if (!tzc_region_is_non_secure(region_index, tzdram_end,
| ^~~~~~~~~~

Fixes: 59c253f92c6c ("plat-stm32mp1: check TZC400 configuration")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: drivers: fix random number reading errors in hisi_trng

Fixes arguments passed to IO_READ32_POLL_TIMEOUT() macro
and missing local variable definition in hisi_trng driver.

Fixes: fb5592f9cfeb

core: drivers: fix random number reading errors in hisi_trng

Fixes arguments passed to IO_READ32_POLL_TIMEOUT() macro
and missing local variable definition in hisi_trng driver.

Fixes: fb5592f9cfeb ("core: drivers: add HiSilicon TRNG implementation")
Signed-off-by: loubaihui <loubaihui1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: drivers: modify debug and error messages in hisi_trng

Modify debug and error messages in hisi_trng.c

Fixes: fb5592f9cfeb ("core: drivers: add HiSilicon TRNG implementation")
Signed-off-by: lo

core: drivers: modify debug and error messages in hisi_trng

Modify debug and error messages in hisi_trng.c

Fixes: fb5592f9cfeb ("core: drivers: add HiSilicon TRNG implementation")
Signed-off-by: loubaihui <loubaihui1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: implement HiSilicon Queue Management (QM) module

The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management

drivers: implement HiSilicon Queue Management (QM) module

The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management module QM is used to interact with software.
Each accelerator module integrates a QM. Software issues tasks to the SQ
(Submmision Queue),and the QM obtains the address of the SQE (Submmision
Queue Element). The BD (Buffer Description, same as SQE) information is
sent to the accelerator. After the task processing is complete, the
accelerator applies for a write-back address from the QM to write back
the SQ.

Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: scmi_server: expose IOD regulators

Replace stubs with recently introduced IO domain regulators
in SCMI server for STM32MP13 variants.

Acked-by: Patrick Delaunay <patrick.delaunay@fos

plat-stm32mp1: scmi_server: expose IOD regulators

Replace stubs with recently introduced IO domain regulators
in SCMI server for STM32MP13 variants.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: scmi_server: simplify regulators identification

Explicitly use a name ID of PMIC regulators identification and a
numerical ID for PWR and stubbed regulators identification while
there

plat-stm32mp1: scmi_server: simplify regulators identification

Explicitly use a name ID of PMIC regulators identification and a
numerical ID for PWR and stubbed regulators identification while
there is only 1 VREFBUF regulator that doesn't need such ID.

Remove string comparison from name to ID conversion for PWR in order
to simplify later use of SDMMC IO domain regulators on STM32MP13
variants.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32mp13: IO domain regulators

Define STM32MP13 IO domains regulators of the stm32mp13f-dk board
based on recently merge stm32mp1_regulator_io driver.

Acked-by: Patrick Delaunay <patrick.dela

dts: stm32mp13: IO domain regulators

Define STM32MP13 IO domains regulators of the stm32mp13f-dk board
based on recently merge stm32mp1_regulator_io driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: IO domain regulators for STM32MP13

Add STM32MP13 IO domains regulators allowing a consumer to
manage IO domains are voltage regulators.

Acked-by: Patrick Delaunay <patrick.delau

drivers: regulator: IO domain regulators for STM32MP13

Add STM32MP13 IO domains regulators allowing a consumer to
manage IO domains are voltage regulators.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: use IO_READ32_POLL_TIMEOUT()

Update stm32mp1_pwr driver to use IO_READ32_POLL_TIMEOUT() macro.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevall

plat-stm32mp1: pwr: use IO_READ32_POLL_TIMEOUT()

Update stm32mp1_pwr driver to use IO_READ32_POLL_TIMEOUT() macro.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: remove test on CFG_DRIVERS_REGULATOR

Remove tests on CFG_DRIVERS_REGULATOR value has the config switch
is always enabled on stm32mp1 platform.

Acked-by: Patrick Delaunay <patric

plat-stm32mp1: pwr: remove test on CFG_DRIVERS_REGULATOR

Remove tests on CFG_DRIVERS_REGULATOR value has the config switch
is always enabled on stm32mp1 platform.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
AP

plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
API functions. This configuration must be appleid at boot time and
when resuming from a system low power state.

This configuration depends on VDD voltage level. It can protected by
a OTP bit (HW2 bit 13) described in the chip reference manual for when
VDD is supplied with a voltage below 2.5V. As stated in the chip
reference manual, enabling HSLV mode with a VDD voltage level above
2.7V may be destructive hence the driver panics in such case.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: HLSV mode for IO domains

Add platform API functions stm32mp_set_hslv_state() and
stm32mp_enable_fixed_vdd_hslv() to configure High Speed Low Voltage
mode of IO domains.

Platf

plat-stm32mp1: syscfg: HLSV mode for IO domains

Add platform API functions stm32mp_set_hslv_state() and
stm32mp_enable_fixed_vdd_hslv() to configure High Speed Low Voltage
mode of IO domains.

Platform function stm32mp_enable_fixed_vdd_hslv() is designed for
fixed voltage IO domains that need to be enable at boot time only
since the supply voltage level never changes.

On STM32MP13 variants, SDMMC IO domains may not be supplied by fixed
voltage VDD but rather by a supply which voltage level can change
at runtime for example to support SD/MMC normative 1.8V and 3.3V voltage
modes. Therefore these IO domains require a runtime configuration
function implemented by stm32mp_set_hslv_state().

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: STM32MP13 dynamic IO compensation

Replace IO compensation API functions
stm32mp_syscfg_enable_io_compensation() and
stm32mp_syscfg_disable_io_compensation() with a new API fun

plat-stm32mp1: syscfg: STM32MP13 dynamic IO compensation

Replace IO compensation API functions
stm32mp_syscfg_enable_io_compensation() and
stm32mp_syscfg_disable_io_compensation() with a new API function
stm32mp_set_io_comp_by_index() dedicated to runtime configuration
of STM32MP13 SDMMC's domains IO compensation only.

On STM32MP15 variant, the configuration is enabled only during
initialization. On STM32MP13 variant, the same feature is also enabled
during initialization but the device embeds 2 more IO domains
(SDMMC1 and SDMMC2) for which the new API function allow runtime
reconfiguration support.

For sake of simplicity, keep related clocks always on.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: compute base address once

Compute SYSCFG virtual address only once.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@f

plat-stm32mp1: syscfg: compute base address once

Compute SYSCFG virtual address only once.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: use U() macro

Use U() macro where applicable in stm32mp1_syscfg.c driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.cheval

plat-stm32mp1: syscfg: use U() macro

Use U() macro where applicable in stm32mp1_syscfg.c driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mmu: fix nsec ddr discovery regarding MEM_AREA_RAM_NSEC

Memory registered as MEM_AREA_RAM_NSEC can be part of the non-secure
shared memory. This change fixes core_mmu_set_discovered_nsec_ddr()

core: mmu: fix nsec ddr discovery regarding MEM_AREA_RAM_NSEC

Memory registered as MEM_AREA_RAM_NSEC can be part of the non-secure
shared memory. This change fixes core_mmu_set_discovered_nsec_ddr()
to not check such memory area do not overlap with non-secure RAM.
This is no issue physical pages from MEM_AREA_RAM_NSEC memory are also
handled and mapped as dynamic non-secure memory by OP-TEE.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: use MEM_AREA_END to detect mapping area end

Change verify_special_mem_areas() prototype to remove the 'len'
argument that is useless since end of the static mapping areas array
is already

core: mm: use MEM_AREA_END to detect mapping area end

Change verify_special_mem_areas() prototype to remove the 'len'
argument that is useless since end of the static mapping areas array
is already defined by a MEM_AREA_END cell.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: MEM_AREA_ROM_SEC maps secure read only cached memory

Define memory area mapping identifier MEM_AREA_ROM_SEC to map read-only
secure cached memory.

Reviewed-by: Jens Wiklander <jens.wiklander@

core: MEM_AREA_ROM_SEC maps secure read only cached memory

Define memory area mapping identifier MEM_AREA_ROM_SEC to map read-only
secure cached memory.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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