core: pta: widevine: Add the init implementation

On the new ChromeOS mediatek platform, we will use the device tree to
pass hardware unique key and the parameters for widevine TAs.

Signed-off-by: Y

core: pta: widevine: Add the init implementation

On the new ChromeOS mediatek platform, we will use the device tree to
pass hardware unique key and the parameters for widevine TAs.

Signed-off-by: Yi Chou <yich@google.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: dts: lx2160a: add memory region

With patch 8a6ca14 (core: arm: get DDR range from embedded DTB)
now DDR ranges are taken from Embedded DTB if enabled and will
ignore DDR ranges defined by regi

core: dts: lx2160a: add memory region

With patch 8a6ca14 (core: arm: get DDR range from embedded DTB)
now DDR ranges are taken from Embedded DTB if enabled and will
ignore DDR ranges defined by register_ddr().
Since Dynamic shared memory and Embedded DTB config is enabled
on LX2160A platforms, need to add the DDR ranges to the DTS.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: fix integer overflow in generic_timer_{handler,start}()

In generic_timer_handler() and generic_timer_start(), read_cntfrq() can
return a pretty large 32-bit number, multiplying that with

core: arm: fix integer overflow in generic_timer_{handler,start}()

In generic_timer_handler() and generic_timer_start(), read_cntfrq() can
return a pretty large 32-bit number, multiplying that with a delay of
1000 ms can overflow. Fix that by casting the result from read_cntfrq()
to a uint64_t to avoid overflow during the calculation.

Fixes: ba6b29591828 ("core: arm64: Add Secure EL1 physical timer framework")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests i

drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests involve only the software key selection
(_SAES_CR_KEYSEL_SOFT) which value is 0 and matches the SoC default
key selection register value.

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: use serial callbacks rx_intr_{en,dis}able()

Use the serial callbacks rx_intr_enable() and rx_intr_disable() to
enable and disable interrupts from the console.

Signed-off-by: Jens Wik

plat-vexpress: use serial callbacks rx_intr_{en,dis}able()

Use the serial callbacks rx_intr_enable() and rx_intr_disable() to
enable and disable interrupts from the console.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: pl011: implement rx_intr_{enable,disable}() callbacks

Implement the optional callbacks to enable and disable receive
interrupts from the PL011 UART. The receive timeout interrupt for the
UART

core: pl011: implement rx_intr_{enable,disable}() callbacks

Implement the optional callbacks to enable and disable receive
interrupts from the PL011 UART. The receive timeout interrupt for the
UART isn't used so don't enable it when initializing the UART.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: serial: add rx_intr_{enable,disable}() callbacks

Add optional callbacks to enable and disable receive interrupts from a
serial device.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org

core: serial: add rx_intr_{enable,disable}() callbacks

Add optional callbacks to enable and disable receive interrupts from a
serial device.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: crypto: fix internal AES-GCM counter implementation

We have several AES-GCM implementations in crypto libraries and
internal. The internal implementation comes in two flavours, with Arm
crypto

core: crypto: fix internal AES-GCM counter implementation

We have several AES-GCM implementations in crypto libraries and
internal. The internal implementation comes in two flavours, with Arm
crypto extensions (CFG_CRYPTO_WITH_CE=y) and a pure software
implementation.

Each block to be encrypted is xored with an encrypted counter block of
equal size (16 bytes). For each block the counter is increased.

Prior to this patch the entire counter block was increased as a 128-bit
integer, but that's not how AES-GCM is defined. In AES-GCM only the
least significant 32 bits of the counter block are increased, leaving
the rest untouched. The difference is only noticeable when the 32 bits
has reached 0xffffffff and wraps to 0x00000000 on next increment. With a
128-bit integer this would propagate into other parts of the block.

Fix this by only incrementing the last 32-bit word in the counter block,
both in the pure software implementation and when using Arm crypto
extensions.

Link: https://github.com/OP-TEE/optee_os/issues/6659
Fixes: 1fca7e269b13 ("core: crypto: add new AES-GCM implementation")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ltc: add missing string_ext.h include

Add a missing include <string_ext.h> needed to fix:
core/lib/libtomcrypt/gcm.c: In function ‘crypto_aes_gcm_dec_final’:
core/lib/libtomcrypt/gcm.c:198:13:

core: ltc: add missing string_ext.h include

Add a missing include <string_ext.h> needed to fix:
core/lib/libtomcrypt/gcm.c: In function ‘crypto_aes_gcm_dec_final’:
core/lib/libtomcrypt/gcm.c:198:13: error: implicit declaration of function ‘consttime_memcmp’ [-Werror=implicit-function-declaration]
198 | if (consttime_memcmp(dst_tag, tag, tag_len) != 0)

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: fix indentation in stm32mp13 clock driver

Fix indentation issues in STM32MP13 clock driver.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Ch

drivers: clk: fix indentation in stm32mp13 clock driver

Fix indentation issues in STM32MP13 clock driver.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: fix some stm32mp13 clock controls

Correct control field definitions for some STM32MP13 clock.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien

drivers: clk: fix some stm32mp13 clock controls

Correct control field definitions for some STM32MP13 clock.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: fix stm32mp13 RNG1 parent clock

Correct RNG1 clock parent list as LSE is not part of according to the
STM32MP13xx reference manual.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clock

drivers: clk: fix stm32mp13 RNG1 parent clock

Correct RNG1 clock parent list as LSE is not part of according to the
STM32MP13xx reference manual.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: list voltages controlled by a GPIO

Implement .supported_voltages() operation in regulator_gpio.c driver
to report voltage levels a level array that is required by scp-firmware
vo

drivers: regulator: list voltages controlled by a GPIO

Implement .supported_voltages() operation in regulator_gpio.c driver
to report voltage levels a level array that is required by scp-firmware
voltage domain module when a regulator-gpio is exposed through an
SCMI voltage domain. This change requires filed voltage_levels_uv[]
array of struct regulator_gpio to be sorted in increasing level value.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ls: correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS

Correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS

Fixes: a8a14b78eef6 ("core: ls: lx2160ardb: Add regions for dynamic shared memory")
F

core: ls: correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS

Correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS

Fixes: a8a14b78eef6 ("core: ls: lx2160ardb: Add regions for dynamic shared memory")
Fixes: 1a1214016d1c ("core: ls: add LX2160A-QDS platform")
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: dt: provide stubbed dt_getprop_as_number()

When compiled with CFG_DT=n link the following error can occur:
aarch64-linux-gnu-ld.bfd: out/arm/core/arch/arm/kernel/boot.o: in function `get_sec_m

core: dt: provide stubbed dt_getprop_as_number()

When compiled with CFG_DT=n link the following error can occur:
aarch64-linux-gnu-ld.bfd: out/arm/core/arch/arm/kernel/boot.o: in function `get_sec_mem_from_manifest':
core/arch/arm/kernel/boot.c:1511: undefined reference to `dt_getprop_as_number'
aarch64-linux-gnu-ld.bfd: core/arch/arm/kernel/boot.c:1519: undefined reference to `dt_getprop_as_number'
aarch64-linux-gnu-ld.bfd: out/arm/core/mm/core_mmu.o: in function `collect_device_mem_ranges':
core/mm/core_mmu.c:982: undefined reference to `dt_getprop_as_number'
aarch64-linux-gnu-ld.bfd: core/mm/core_mmu.c:993: undefined reference to `dt_getprop_as_number'

Fix this by adding a stubbed version of dt_getprop_as_number() when
CFG_DT=n.

Link: https://github.com/OP-TEE/optee_os/issues/6537
Fixes: 4e45454a85d3 ("core: add dt_getprop_as_number()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: ffa: add notifications with SPMC at S-EL2 or EL3

Adds support for asynchronous notifications via FF-A with SPMC at S-EL2
or EL3.

The SPMC is probed using FFA_FEATURES(FFA_NOTIFICATION_SET) to

core: ffa: add notifications with SPMC at S-EL2 or EL3

Adds support for asynchronous notifications via FF-A with SPMC at S-EL2
or EL3.

The SPMC is probed using FFA_FEATURES(FFA_NOTIFICATION_SET) to see if
the SPMC is support FF-A notifications.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: hfic: fix HF_INTERRUPT HVC calls

The HF_INTERRUPT HVC calls has until now not been completely correct.
HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the
current CPU whil

core: hfic: fix HF_INTERRUPT HVC calls

The HF_INTERRUPT HVC calls has until now not been completely correct.
HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the
current CPU while HF_INTERRUPT_RECONFIGURE is used to globally enable a
physical interrupt. So update the HFIC callbacks accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: move hafnium.h into hfic.c

hafnium.h is only included from hfic.c so move the content into that
file instead. Comments trying to describe the paravirtualized interface
are removed and replaced

core: move hafnium.h into hfic.c

hafnium.h is only included from hfic.c so move the content into that
file instead. Comments trying to describe the paravirtualized interface
are removed and replaced by a link to official documentation.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: exit with native interrupts unmasked

When exiting using the main exit/re-entry loop in
ffa_msg_send_direct_resp(), unmask native interrupts before the SMC
instruction and mask them again

core: ffa: exit with native interrupts unmasked

When exiting using the main exit/re-entry loop in
ffa_msg_send_direct_resp(), unmask native interrupts before the SMC
instruction and mask them again on re-entry. This guarantees that native
(aka secure) interrupts are not pending during exit. This also means
that when entering with FFA_INTERRUPT the interrupt will be handled
before thread_spmc_msg_recv() so there is no need to call
interrupt_main_handler() from thread_spmc_msg_recv() any longer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64.h: add DAIFBIT_{NATIVE,FOREIGN}_INTR

Adds the two defines DAIFBIT_NATIVE_INTR and DAIFBIT_FOREIGN_INTR based
on DAIFBIT_IRQ and DAIFBIT_FIQ analogous with how
THREAD_EXCP_FOREIGN_INTR an

core: arm64.h: add DAIFBIT_{NATIVE,FOREIGN}_INTR

Adds the two defines DAIFBIT_NATIVE_INTR and DAIFBIT_FOREIGN_INTR based
on DAIFBIT_IRQ and DAIFBIT_FIQ analogous with how
THREAD_EXCP_FOREIGN_INTR and THREAD_EXCP_NATIVE_INTR are defined.

DAIFBIT_NATIVE_INTR and DAIFBIT_FOREIGN_INTR can be used in assembly
instead of using #ifdef CFG_CORE_IRQ_IS_NATIVE_INTR.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-k3: drivers: sec_proxy: increment while reading trail bytes

The trail bytes from the secure proxy driver were being overwritten,
increase the count each time to not overwrite the existing data

plat-k3: drivers: sec_proxy: increment while reading trail bytes

The trail bytes from the secure proxy driver were being overwritten,
increase the count each time to not overwrite the existing data and not
get the end data corrupted from secure proxy.

Fixes: cf20f0a4f77e ("plat-k3: drivers: Add secure proxy driver for communication with System Controller")
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>

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plat-stm32mp2: default enable embedded test

Set CFG_ENABLE_EMBEDDED_TESTS to y for STM32MP2x platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carrier

plat-stm32mp2: default enable embedded test

Set CFG_ENABLE_EMBEDDED_TESTS to y for STM32MP2x platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: allow up to 8GB of external RAM

Default enable CFG_CORE_LARGE_PHYS_ADDR and set CFG_CORE_ARM64_PA_BITS
to 34 to allow external DDR sizes up to 8GB. This change does not permit
OP-TEE

plat-stm32mp2: allow up to 8GB of external RAM

Default enable CFG_CORE_LARGE_PHYS_ADDR and set CFG_CORE_ARM64_PA_BITS
to 34 to allow external DDR sizes up to 8GB. This change does not permit
OP-TEE to execute above 32bit virtual addresses but allows OP-TEE
to accept and map shared memories of physical addresses above 4GByte.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_rstc: add the function to control sama7g5's USB reset

In sama7g5, USB POR is controlled by register RSTC_GRSTR.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fori

drivers: atmel_rstc: add the function to control sama7g5's USB reset

In sama7g5, USB POR is controlled by register RSTC_GRSTR.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_tcb: update to compatible with sama7g5

Update the clocks for sama7g5's TC.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
A

drivers: atmel_tcb: update to compatible with sama7g5

Update the clocks for sama7g5's TC.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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