| dcad1800 | 12-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add nex_*init-calls
Add nex_*init-calls for drivers and services that resides in the nexus in case of virtualization. In case of virtualization the init-calls are based on final calls, while o
core: add nex_*init-calls
Add nex_*init-calls for drivers and services that resides in the nexus in case of virtualization. In case of virtualization the init-calls are based on final calls, while otherwise are the same as the non-nex counterpart.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 3d52f27c | 12-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: move multi_core_panic_handler into __nex_data
Multi core panic interrupts are delivered on all cores on panic. For this to work reliably with CFG_NS_VIRTUALIZATION=y make sure that multi_core_
core: move multi_core_panic_handler into __nex_data
Multi core panic interrupts are delivered on all cores on panic. For this to work reliably with CFG_NS_VIRTUALIZATION=y make sure that multi_core_panic_handler is located in nexus memory.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| ba4f5940 | 12-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: add is_nexus() and refactor is_unpaged()
Add the function is_nexus() to tell if an address is an address available to the nexus when non-secure virtualization is enabled (CFG_NS_VIRTUALIZATION
core: add is_nexus() and refactor is_unpaged()
Add the function is_nexus() to tell if an address is an address available to the nexus when non-secure virtualization is enabled (CFG_NS_VIRTUALIZATION=y). The function is stubbed to return true for non-null arguments if non-secure virtualization isn't enabled, else false.
Make the argument for is_unpaged() const void * for consistency with the is_nexus() function. The stubbed version of is_unpaged() when paging isn't enabled is updated to perform a NULL check on the argument.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| d99b271a | 13-Feb-2024 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: se050: fix default configuration for the SE applet
Invalid character was merged in the fixed commit.
Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet") Sig
drivers: se050: fix default configuration for the SE applet
Invalid character was merged in the fixed commit.
Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet") Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 97452933 | 24-Jan-2024 |
Niklas Kirschall <niki.nice1203@gmail.com> |
core: kernel: fix typo in huk_subkey.h inline comment
Fix a typo in `huk_subkey.h` inline comment where TEE_SUCCES should be TEE_SUCCESS.
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> S
core: kernel: fix typo in huk_subkey.h inline comment
Fix a typo in `huk_subkey.h` inline comment where TEE_SUCCES should be TEE_SUCCESS.
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Niklas Kirschall <niki.nice1203@gmail.com>
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| a7400fcd | 07-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: fix lock in virt_add_cookie_to_current_guest()
Prior to this patch was virt_add_cookie_to_current_guest() only masking interrupts while adding a shared memory cookie to the list of cookie
core: arm: fix lock in virt_add_cookie_to_current_guest()
Prior to this patch was virt_add_cookie_to_current_guest() only masking interrupts while adding a shared memory cookie to the list of cookies. Proper locking is needed to serialize access to the cookie list, replace the interrupt masking with a cpu_spin_lock_xsave().
Fixes: a65dd3a6b64d ("core: spmc: support virtualization with SPMC at S-EL1") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 89853006 | 30-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: crypto: fix crypto_asym_get_ecc_keypair_ops() stub
Correct definition of crypto_asym_get_ecc_keypair_ops() stub inline function when CFG_CRYPTO_ECC is disabled. The definition used a wrong fun
core: crypto: fix crypto_asym_get_ecc_keypair_ops() stub
Correct definition of crypto_asym_get_ecc_keypair_ops() stub inline function when CFG_CRYPTO_ECC is disabled. The definition used a wrong function label.
Fixes: 5516c6cd78da ("core: ecc: support the crypto driver") Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ad194957 | 13-Oct-2023 |
Yi Chou <yich@google.com> |
core: pta: widevine: Add the init implementation
On the new ChromeOS mediatek platform, we will use the device tree to pass hardware unique key and the parameters for widevine TAs.
Signed-off-by: Y
core: pta: widevine: Add the init implementation
On the new ChromeOS mediatek platform, we will use the device tree to pass hardware unique key and the parameters for widevine TAs.
Signed-off-by: Yi Chou <yich@google.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 64086346 | 06-Feb-2024 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: dts: lx2160a: add memory region
With patch 8a6ca14 (core: arm: get DDR range from embedded DTB) now DDR ranges are taken from Embedded DTB if enabled and will ignore DDR ranges defined by regi
core: dts: lx2160a: add memory region
With patch 8a6ca14 (core: arm: get DDR range from embedded DTB) now DDR ranges are taken from Embedded DTB if enabled and will ignore DDR ranges defined by register_ddr(). Since Dynamic shared memory and Embedded DTB config is enabled on LX2160A platforms, need to add the DDR ranges to the DTS.
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 439c5ecb | 31-Jan-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: fix integer overflow in generic_timer_{handler,start}()
In generic_timer_handler() and generic_timer_start(), read_cntfrq() can return a pretty large 32-bit number, multiplying that with
core: arm: fix integer overflow in generic_timer_{handler,start}()
In generic_timer_handler() and generic_timer_start(), read_cntfrq() can return a pretty large 32-bit number, multiplying that with a delay of 1000 ms can overflow. Fix that by casting the result from read_cntfrq() to a uint64_t to avoid overflow during the calculation.
Fixes: ba6b29591828 ("core: arm64: Add Secure EL1 physical timer framework") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c83a542f | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: crypto: stm32: fix SAES key selection
Correction selection of key in STM32 SAES driver that missed a left bit shift operation. The bug was not experienced before as current platform tests i
drivers: crypto: stm32: fix SAES key selection
Correction selection of key in STM32 SAES driver that missed a left bit shift operation. The bug was not experienced before as current platform tests involve only the software key selection (_SAES_CR_KEYSEL_SOFT) which value is 0 and matches the SoC default key selection register value.
Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support") Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b066e825 | 02-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
plat-vexpress: use serial callbacks rx_intr_{en,dis}able()
Use the serial callbacks rx_intr_enable() and rx_intr_disable() to enable and disable interrupts from the console.
Signed-off-by: Jens Wik
plat-vexpress: use serial callbacks rx_intr_{en,dis}able()
Use the serial callbacks rx_intr_enable() and rx_intr_disable() to enable and disable interrupts from the console.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 6d9ff02e | 02-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: pl011: implement rx_intr_{enable,disable}() callbacks
Implement the optional callbacks to enable and disable receive interrupts from the PL011 UART. The receive timeout interrupt for the UART
core: pl011: implement rx_intr_{enable,disable}() callbacks
Implement the optional callbacks to enable and disable receive interrupts from the PL011 UART. The receive timeout interrupt for the UART isn't used so don't enable it when initializing the UART.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| e934bfa4 | 02-Feb-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: serial: add rx_intr_{enable,disable}() callbacks
Add optional callbacks to enable and disable receive interrupts from a serial device.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org
core: serial: add rx_intr_{enable,disable}() callbacks
Add optional callbacks to enable and disable receive interrupts from a serial device.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| fcabe15c | 31-Jan-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: crypto: fix internal AES-GCM counter implementation
We have several AES-GCM implementations in crypto libraries and internal. The internal implementation comes in two flavours, with Arm crypto
core: crypto: fix internal AES-GCM counter implementation
We have several AES-GCM implementations in crypto libraries and internal. The internal implementation comes in two flavours, with Arm crypto extensions (CFG_CRYPTO_WITH_CE=y) and a pure software implementation.
Each block to be encrypted is xored with an encrypted counter block of equal size (16 bytes). For each block the counter is increased.
Prior to this patch the entire counter block was increased as a 128-bit integer, but that's not how AES-GCM is defined. In AES-GCM only the least significant 32 bits of the counter block are increased, leaving the rest untouched. The difference is only noticeable when the 32 bits has reached 0xffffffff and wraps to 0x00000000 on next increment. With a 128-bit integer this would propagate into other parts of the block.
Fix this by only incrementing the last 32-bit word in the counter block, both in the pure software implementation and when using Arm crypto extensions.
Link: https://github.com/OP-TEE/optee_os/issues/6659 Fixes: 1fca7e269b13 ("core: crypto: add new AES-GCM implementation") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b4d33ca3 | 31-Jan-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ltc: add missing string_ext.h include
Add a missing include <string_ext.h> needed to fix: core/lib/libtomcrypt/gcm.c: In function ‘crypto_aes_gcm_dec_final’: core/lib/libtomcrypt/gcm.c:198:13:
core: ltc: add missing string_ext.h include
Add a missing include <string_ext.h> needed to fix: core/lib/libtomcrypt/gcm.c: In function ‘crypto_aes_gcm_dec_final’: core/lib/libtomcrypt/gcm.c:198:13: error: implicit declaration of function ‘consttime_memcmp’ [-Werror=implicit-function-declaration] 198 | if (consttime_memcmp(dst_tag, tag, tag_len) != 0)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 64a52f9d | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: fix indentation in stm32mp13 clock driver
Fix indentation issues in STM32MP13 clock driver.
Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13") Reviewed-by: Gatien Ch
drivers: clk: fix indentation in stm32mp13 clock driver
Fix indentation issues in STM32MP13 clock driver.
Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13") Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| f4dba325 | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: fix some stm32mp13 clock controls
Correct control field definitions for some STM32MP13 clock.
Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13") Reviewed-by: Gatien
drivers: clk: fix some stm32mp13 clock controls
Correct control field definitions for some STM32MP13 clock.
Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13") Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| a32213b8 | 26-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: fix stm32mp13 RNG1 parent clock
Correct RNG1 clock parent list as LSE is not part of according to the STM32MP13xx reference manual.
Fixes: 5436921f6866 ("clk: stm32mp13: add all clock
drivers: clk: fix stm32mp13 RNG1 parent clock
Correct RNG1 clock parent list as LSE is not part of according to the STM32MP13xx reference manual.
Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13") Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| d615a7e6 | 23-Jan-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: list voltages controlled by a GPIO
Implement .supported_voltages() operation in regulator_gpio.c driver to report voltage levels a level array that is required by scp-firmware vo
drivers: regulator: list voltages controlled by a GPIO
Implement .supported_voltages() operation in regulator_gpio.c driver to report voltage levels a level array that is required by scp-firmware voltage domain module when a regulator-gpio is exposed through an SCMI voltage domain. This change requires filed voltage_levels_uv[] array of struct regulator_gpio to be sorted in increasing level value.
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| bbc33e2a | 30-Jan-2024 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: ls: correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS
Correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS
Fixes: a8a14b78eef6 ("core: ls: lx2160ardb: Add regions for dynamic shared memory") F
core: ls: correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS
Correct CFG_CORE_ARM64_PA_BITS for LX2160A-RDB/QDS
Fixes: a8a14b78eef6 ("core: ls: lx2160ardb: Add regions for dynamic shared memory") Fixes: 1a1214016d1c ("core: ls: add LX2160A-QDS platform") Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 5a982d0e | 30-Jan-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: dt: provide stubbed dt_getprop_as_number()
When compiled with CFG_DT=n link the following error can occur: aarch64-linux-gnu-ld.bfd: out/arm/core/arch/arm/kernel/boot.o: in function `get_sec_m
core: dt: provide stubbed dt_getprop_as_number()
When compiled with CFG_DT=n link the following error can occur: aarch64-linux-gnu-ld.bfd: out/arm/core/arch/arm/kernel/boot.o: in function `get_sec_mem_from_manifest': core/arch/arm/kernel/boot.c:1511: undefined reference to `dt_getprop_as_number' aarch64-linux-gnu-ld.bfd: core/arch/arm/kernel/boot.c:1519: undefined reference to `dt_getprop_as_number' aarch64-linux-gnu-ld.bfd: out/arm/core/mm/core_mmu.o: in function `collect_device_mem_ranges': core/mm/core_mmu.c:982: undefined reference to `dt_getprop_as_number' aarch64-linux-gnu-ld.bfd: core/mm/core_mmu.c:993: undefined reference to `dt_getprop_as_number'
Fix this by adding a stubbed version of dt_getprop_as_number() when CFG_DT=n.
Link: https://github.com/OP-TEE/optee_os/issues/6537 Fixes: 4e45454a85d3 ("core: add dt_getprop_as_number()") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 55cd94d1 | 07-Dec-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ffa: add notifications with SPMC at S-EL2 or EL3
Adds support for asynchronous notifications via FF-A with SPMC at S-EL2 or EL3.
The SPMC is probed using FFA_FEATURES(FFA_NOTIFICATION_SET) to
core: ffa: add notifications with SPMC at S-EL2 or EL3
Adds support for asynchronous notifications via FF-A with SPMC at S-EL2 or EL3.
The SPMC is probed using FFA_FEATURES(FFA_NOTIFICATION_SET) to see if the SPMC is support FF-A notifications.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 49655078 | 07-Dec-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: hfic: fix HF_INTERRUPT HVC calls
The HF_INTERRUPT HVC calls has until now not been completely correct. HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the current CPU whil
core: hfic: fix HF_INTERRUPT HVC calls
The HF_INTERRUPT HVC calls has until now not been completely correct. HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the current CPU while HF_INTERRUPT_RECONFIGURE is used to globally enable a physical interrupt. So update the HFIC callbacks accordingly.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| e37b526d | 07-Dec-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: move hafnium.h into hfic.c
hafnium.h is only included from hfic.c so move the content into that file instead. Comments trying to describe the paravirtualized interface are removed and replaced
core: move hafnium.h into hfic.c
hafnium.h is only included from hfic.c so move the content into that file instead. Comments trying to describe the paravirtualized interface are removed and replaced by a link to official documentation.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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