core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updat

core: gic: wait for writes to propagate

Some updates to the GIC redistributor takes a while before they are
visible to all agents in the system. The GICR_CTLR_RWP bit in GICR_CTLR
indicates if updates are still being propagated. Add checks for this
after each write to GICR_ICENABLER0 to make sure that the system is
consistent before continuing.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be sync

core: gic: support to configure PPI interrupts

Add support to configure PPI interrupts (assigning to Secure Group 1
etc). Since PPIs are per CPU interrupts as SGIs their configuration
should be synchronized to all CPUs in the same way. Add support to
synchronize needed PPI configuration to other CPUs.

The configuration that needs to be synchronized to other CPUs should
ideally not be changed once the primary CPU has booted. So add a check
in gic_op_enable() to catch this.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: call init_multi_core_panic_handler() earlier

Call init_multi_core_panic_handler() slightly earlier in during boot
using nex_driver_init_late() instead of boot_final(). This avoids with a
comin

core: call init_multi_core_panic_handler() earlier

Call init_multi_core_panic_handler() slightly earlier in during boot
using nex_driver_init_late() instead of boot_final(). This avoids with a
coming assert() in the GIC driver to check that SGI and PPI can't be
configured after or at nex_release_init_resource().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit

core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit (V), which is not proper way when clearing PTE. Fix it by only
honoring pte_bits parameter, which may be constructed in
mattr_to_pte_bits().

The core_mmu_ptp_create() is used to create non-leaf PTE, which points
to the next level of the page table. According to RISC-V privilege Spec,
non-leaf PTE only needs V bit. Therefore, we just give the V bit to
core_mmu_pte_create() when we want to create non-leaf PTE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Rename mattr_to_perms() to mattr_to_pte_bits()

This function not only constructs permission bits (R, W, X) of PTE, but
also other bits such as valid bit (V), user bit (U), global bit (G

core: riscv: Rename mattr_to_perms() to mattr_to_pte_bits()

This function not only constructs permission bits (R, W, X) of PTE, but
also other bits such as valid bit (V), user bit (U), global bit (G),
accessed bit (A), and dirty bit (D). Rename it to mattr_to_pte_bits()
for greater readability.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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drivers: clk: clk-stm32mp13: round up VCO to the nearest frequency

Round up the vco clock to avoid unexpected clock rate:
- 999,999,023 Hz instead 1,000,000,000 Hz
- 417,755,859 Hz instead 417,800,0

drivers: clk: clk-stm32mp13: round up VCO to the nearest frequency

Round up the vco clock to avoid unexpected clock rate:
- 999,999,023 Hz instead 1,000,000,000 Hz
- 417,755,859 Hz instead 417,800,000 Hz

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired

If an oscillator is not wired we shouldn't gate it to avoid a panic.
For example the external LSE oscillator may not be supported

drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired

If an oscillator is not wired we shouldn't gate it to avoid a panic.
For example the external LSE oscillator may not be supported on a board
in which case node named clk-lse is disabled in the board DTS file.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: clk-stm32mp13: add ADC and SPI clocks

Add definition of ADCs and SPI buses clocks for platform variant
STM32MP13.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed

drivers: clk: clk-stm32mp13: add ADC and SPI clocks

Add definition of ADCs and SPI buses clocks for platform variant
STM32MP13.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mmu: add MEM_AREA_ROM_SEC in check_mem_map()

Handle MEM_AREA_ROM_SEC in check_mem_map() switch case to prevent OP-TEE
core from panicking when such area is mapped.

Fixes: fc7e0cc38b99 ("core:

core: mmu: add MEM_AREA_ROM_SEC in check_mem_map()

Handle MEM_AREA_ROM_SEC in check_mem_map() switch case to prevent OP-TEE
core from panicking when such area is mapped.

Fixes: fc7e0cc38b99 ("core: MEM_AREA_ROM_SEC maps secure read only cached memory")
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: add CAAM key support for DH

Add CAAM key support for DH.
Add DH black key support for shared secret generation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sa

drivers: caam: add CAAM key support for DH

Add CAAM key support for DH.
Add DH black key support for shared secret generation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for ECC

Add CAAM key support for ECC.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for ECC

Add CAAM key support for ECC.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for DSA

Add CAAM key support for DSA.
Add DSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for DSA

Add CAAM key support for DSA.
Add DSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for RSA

Add CAAM key support for RSA.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for RSA

Add CAAM key support for RSA.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key driver

Add CAAM key driver and CAAM key object.
Add key blob encapsulation methods.
Add key serialize and deserialize functions for bignum encapsulation.

Signed-off-by:

drivers: caam: add CAAM key driver

Add CAAM key driver and CAAM key object.
Add key blob encapsulation methods.
Add key serialize and deserialize functions for bignum encapsulation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: fix DSA_DUMPDESC macro

Fix typo in DSA_DUMPDESC and replace MP_TRACE with DSA_TRACE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier

drivers: caam: fix DSA_DUMPDESC macro

Fix typo in DSA_DUMPDESC and replace MP_TRACE with DSA_TRACE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: add missing header

Add missing caam_status.h include.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: caam: add class field to FIFO_ST macro

Add class field to FIFO_ST macro and update existing
usage of FIFO_ST with required CLASS.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Sig

drivers: caam: add class field to FIFO_ST macro

Add class field to FIFO_ST macro and update existing
usage of FIFO_ST with required CLASS.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: move CFG_CORE_BIGNUM_MAX_BITS default definition

Move CFG_CORE_BIGNUM_MAX_BITS definition to mk/crypto.mk to allow crypto
drivers to override the default value.

Signed-off-by: Clement Faure <

core: move CFG_CORE_BIGNUM_MAX_BITS default definition

Move CFG_CORE_BIGNUM_MAX_BITS definition to mk/crypto.mk to allow crypto
drivers to override the default value.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add RIFSC compatible to RIFSC node in stm32mp251.dtsi

Add the compatible to allow a match between the driver and the node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.co

dts: stm32: add RIFSC compatible to RIFSC node in stm32mp251.dtsi

Add the compatible to allow a match between the driver and the node.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: Add RIFSC configuration support for stm32mp257f-ev1

Defines RIFSC configuration for stm32mp257f-ev1 board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by:

dts: stm32: Add RIFSC configuration support for stm32mp257f-ev1

Defines RIFSC configuration for stm32mp257f-ev1 board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: enable RIFSC driver

Enable the RIFSC driver for STM32MP2x platforms

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carr

plat-stm32mp2: conf: enable RIFSC driver

Enable the RIFSC driver for STM32MP2x platforms

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add RIFSC to default bindings config for STM32MP25

The RIFSC header is now part of default bindings header file for
STM32MP25.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.

dt-bindings: add RIFSC to default bindings config for STM32MP25

The RIFSC header is now part of default bindings header file for
STM32MP25.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add RIFSC bindings

Add bindings for the RIFSC configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.co

dt-bindings: add RIFSC bindings

Add bindings for the RIFSC configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: add stm32 RIFSC support

Add the RIFSC new driver support.

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed

drivers: add stm32 RIFSC support

Add the RIFSC new driver support.

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.

This driver parses the RIFSC device tree configuration and applies
it to put the firewall in place. Therefore, the device tree is
mandatory.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: support RIF driver

Default enable RIF driver for STM32MP2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.car

plat-stm32mp2: conf: support RIF driver

Default enable RIF driver for STM32MP2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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