drivers: nvmem: add nvmem-huk driver

This driver is meant to read the OTP unique hardware key from a
NVMEM controller. It uses the nvmem framework to read the NVMEM
cells from the device tree.

Sign

drivers: nvmem: add nvmem-huk driver

This driver is meant to read the OTP unique hardware key from a
NVMEM controller. It uses the nvmem framework to read the NVMEM
cells from the device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: nvmem: add nvmem-die-id driver

This driver is meant to read the die id from a NVMEM controller.
It uses the nvmem framework to read the NVMEM cells from the
device tree.

Signed-off-by: Tho

drivers: nvmem: add nvmem-die-id driver

This driver is meant to read the die id from a NVMEM controller.
It uses the nvmem framework to read the NVMEM cells from the
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Implement semihosting based console driver for log

Implement a simple console driver which uses semihosting operations to
read/write the trace messages. There are two paths to output the tr

drivers: Implement semihosting based console driver for log

Implement a simple console driver which uses semihosting operations to
read/write the trace messages. There are two paths to output the trace
messages:
- If the caller of semihosting_console_init() provides the path of the
file, the driver will try to open that file, and output the log to
that host side file.
- If the caller of semihosting_console_init() does not provide the path
of the file, the driver will connect the console to the host debug
console directly.

If CFG_SEMIHOSTING_CONSOLE is enabled, OP-TEE will try to initialize the
semihosting console driver by given CFG_SEMIHOSTING_CONSOLE_FILE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://githu

core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://github.com/riscv-non-isa/riscv-semihosting

Add semihosting.S into RISC-V kernel folder to implement the trap
instruction sequence.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: Add semihosting functions

Semihosting is a mechanism that enables target to communicate and use
I/O facilities on a host computer which is running a debugger, such as
GDB. The I/O faci

core: kernel: Add semihosting functions

Semihosting is a mechanism that enables target to communicate and use
I/O facilities on a host computer which is running a debugger, such as
GDB. The I/O facilities include character {read|write} {from|to} the
semihosting host side console or a file. In other words, OP-TEE OS can
output log to the host side console or the host side file, if there is a
semihosting host and OP-TEE OS requests the semihosting operations to
that host.

If CFG_SEMIHOSTING is enabled, some semihosting functions will be
compiled into OP-TEE kernel, including:
- semihosting_sys_readc()
- semihosting_sys_writec()
- semihosting_open()
- semihosting_read()
- semihosting_write()
- semihosting_close()

Note that the architectures which support semihosting should provide
their implementation of __do_semihosting(), which performs semihosting
instruction to raise the semihosting request.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: implement plat_get_freq() for sama7g5

Sama7g5 platform does not have support for the ARM generic timer
extension, so plat_get_freq() needs to be updated to be able to
probe clocks early us

plat-sam: implement plat_get_freq() for sama7g5

Sama7g5 platform does not have support for the ARM generic timer
extension, so plat_get_freq() needs to be updated to be able to
probe clocks early using the device tree as for the sama5d2.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: register additional sama7g5 clocks for SCMI usage

- Add the macro definitions for each SCMI clock.
- Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Thomas Perrot <thomas

plat-sam: register additional sama7g5 clocks for SCMI usage

- Add the macro definitions for each SCMI clock.
- Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: register sama7g5 clocks for SCMI usage

Add the macro definitions for each SCMI clock.
Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ac

plat-sam: register sama7g5 clocks for SCMI usage

Add the macro definitions for each SCMI clock.
Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: make API function description more consistent

Change inline description comments of clock framework API functions,
macros and structures to be more consistent.

Reviewed-by: Gatien Che

drivers: clk: make API function description more consistent

Change inline description comments of clock framework API functions,
macros and structures to be more consistent.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: get stm32mp13 PLL output clock duty cycle

Implement get_duty_cycle clock operation for STM32MP13 PLL output clocks.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Sign

drivers: clk: get stm32mp13 PLL output clock duty cycle

Implement get_duty_cycle clock operation for STM32MP13 PLL output clocks.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: set stm32mp13 clock flags

On STM32MP13 SoC, setting PLL1P, PLL1P_DIV, MPU, AXI and MLAHB clocks
rate must be handled from their respective parent clock. Set flag
CLK_SET_RATE_PARENT fo

drivers: clk: set stm32mp13 clock flags

On STM32MP13 SoC, setting PLL1P, PLL1P_DIV, MPU, AXI and MLAHB clocks
rate must be handled from their respective parent clock. Set flag
CLK_SET_RATE_PARENT for these clocks.

On STM32MP13 SoC, MPU, AXI and MLAHB clocks are internal bus clocks
that must not be disabled even when we re-parent them. Set flag
CLK_SET_PARENT_PRE_ENABLE for these clocks.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: pre-enable new parent on clock re-parent

Add new clock flag CLK_SET_PARENT_PRE_ENABLE for when an already
enabled clock is re-parented and the new parent clock must be enabled
before w

drivers: clk: pre-enable new parent on clock re-parent

Add new clock flag CLK_SET_PARENT_PRE_ENABLE for when an already
enabled clock is re-parented and the new parent clock must be enabled
before we switch of parents.

This is needed for some system clocks that cannot be disabled, for
example an interconnect AXI bus clock or a CPU clock.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: get linear rates description

Implement clk_get_rates_steps() clock API function to get the supported
clock rates description as a triplet min/max/step. This function can be
used in the

drivers: clk: get linear rates description

Implement clk_get_rates_steps() clock API function to get the supported
clock rates description as a triplet min/max/step. This function can be
used in the scope of SCMI communication where a clock can report a
linear rate list without listing all supported clock is an array
which size could be quite big.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: enable clock on rate change

Add new clock flag CLK_SET_RATE_UNGATE for clocks that must be
enabled in order to change their rate.

Reviewed-by: Gatien Chevallier <gatien.chevallier@fos

drivers: clk: enable clock on rate change

Add new clock flag CLK_SET_RATE_UNGATE for clocks that must be
enabled in order to change their rate.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: change parent clock rate if needed

Add clock flag CLK_SET_RATE_PARENT for clocks for which rate change
request must be propagated to the parent clock.

Reviewed-by: Gatien Chevallier <

drivers: clk: change parent clock rate if needed

Add clock flag CLK_SET_RATE_PARENT for clocks for which rate change
request must be propagated to the parent clock.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: Get duty cycle from parent clock

Add CLK_DUTY_CYCLE_PARENT clock flag for clock which duty cycle
information needs to be retrieved for the clock parent.

Reviewed-by: Gatien Chevallier

drivers: clk: Get duty cycle from parent clock

Add CLK_DUTY_CYCLE_PARENT clock flag for clock which duty cycle
information needs to be retrieved for the clock parent.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: Add clock duty cycle

Implement reading a clock duty cycle with new clock API function
clk_get_duty_cycle() and clock operation handle ::clk_get_duty_cycle.
When a clock does not provid

drivers: clk: Add clock duty cycle

Implement reading a clock duty cycle with new clock API function
clk_get_duty_cycle() and clock operation handle ::clk_get_duty_cycle.
When a clock does not provide the operation, it is assumed that the clock
has a 50% duty cycle.

Clock duty cycle information is used for example for some analog-digital
conversion peripheral. This new API function is also expected to be used
by SCMI clock service introduced in the SCMI specification v3.2 [1]
this allow to expose duty cycle service to SCMI clients.

Link: https://developer.arm.com/documentation/den0056/e/ [1]
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: add pm support on stm32mp25

Add support of low power mode on stm32mp25 and perform the needed OP-TEE
bookkeeping before PSCI executes a power management sequence, with the 3
hooks cal

plat-stm32mp2: add pm support on stm32mp25

Add support of low power mode on stm32mp25 and perform the needed OP-TEE
bookkeeping before PSCI executes a power management sequence, with the 3
hooks called by TF-A SPD :
- thread_system_off_handler()
- thread_cpu_resume_handler()
- thread_cpu_suspend_handler()

On PSCI system off request, the STPMIC25 driver need to configure the
regulators properly to handle the always on domain with the board
configuration (PMIC switch OFF, with coin cell, or standby DDR off).

For PSCI suspend requests, the STM32MP25 family supports 5 power levels
in the PSCI topology to handle the regulators configuration done in STPMIC2
for low poser modes, in particular to differentiate the tension for LP and
the LPLV modes:

power level (System mode for a0= Max power level powered down)
--------------------------------------------------------------------------
0: CPU1 core#0 or core#1 (Stop1 or LP-Stop1)
1: D1 domain (LPLV-Stop1)
2: LPLV D1 (Stop2 or LP-Stop2)
3: D2 (LPLV-Stop2)
4: LPLV D2 (Standby)
5: MAX (PowerOff: Standby or VBat)

The hook calls pm_change_state with generic HINT for inform STM32MP25
drivers to operation to performed on suspend/resume:
- PM_HINT_CLOCK_STATE
the IP clock will be deactivated, the pending operation should stop,
cleanup operation can be done on HW to prepare the clock freeze
(optional support by driver)
- PM_HINT_CONTEXT_STATE
called for System level standby when the IP configuration is lost.
The state of each device must be saved in RAM which is preserved
(DDR in self-refresh, mandatory)

Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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core: pm: add macro for PM_HINT_STATE access

Add helper macros to read and test the power state hints provided by
the platform during power management state transitions.

Reviewed-by: Etienne Carrie

core: pm: add macro for PM_HINT_STATE access

Add helper macros to read and test the power state hints provided by
the platform during power management state transitions.

Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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plat-sam: fix static shared memory address and size

Disable the dynamic shared memory allocation that isn't used on SAM
platforms, otherwise the following issue occurs, since the commit
8a6ca1480ddc

plat-sam: fix static shared memory address and size

Disable the dynamic shared memory allocation that isn't used on SAM
platforms, otherwise the following issue occurs, since the commit
8a6ca1480ddc ("core: arm: get DDR range from embedded DTB"):

I/TC: Embedded DTB found
E/TC:0 0 check_phys_mem_is_outside:409 Non-sec mem (0x20800000:0x1f800000) overlaps map (type 18 0x21400000:0x1000)
E/TC:0 0 Panic at core/mm/core_mmu.c:413 <check_phys_mem_is_outside>
E/TC:0 0 TEE load address @ 0x20000000
E/TC:0 0 Call stack:
E/TC:0 0 0x20005655 print_kernel_stack at core/arch/arm/kernel/unwind_arm32.c:109
E/TC:0 0 0x2001c52d __do_panic at core/kernel/panic.c:80
E/TC:0 0 0x200276c1 check_phys_mem_is_outside at core/mm/core_mmu.c:413
E/TC:0 0 0x2002780f core_mmu_set_discovered_nsec_ddr at core/mm/core_mmu.c:481
E/TC:0 0 0x200050b3 discover_nsec_memory at core/arch/arm/kernel/boot.c:1055
E/TC:0 0 0x20005247 boot_init_primary_late at core/arch/arm/kernel/boot.c:1210
E/TC:0 0 0x200001fc reset_primary at core/arch/arm/kernel/entry_a32.S:532

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-mediatek: add support for MT7988 SoC

Add OP-TEE support for the MT7988 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by:

plat-mediatek: add support for MT7988 SoC

Add OP-TEE support for the MT7988 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.

drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support generic clock for sama7g5

Add a mux table for select from different generic clock source.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fori

drivers: clk: sam: update to support generic clock for sama7g5

Add a mux table for select from different generic clock source.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support main system bus clock for sama7g5

Add functions for configuring sama7g5 main system bus clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome

drivers: clk: sam: update to support main system bus clock for sama7g5

Add functions for configuring sama7g5 main system bus clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...