core: introduce CFG_NOTIF_TEST_WD

Add CFG_NOTIF_TEST_WD to control if the notification based test watchdog
should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: introduce CFG_NOTIF_TEST_WD

Add CFG_NOTIF_TEST_WD to control if the notification based test watchdog
should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@lina

core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: notif: assert callback is unpaged

Add an assert that the atomic_cb() pointer in notif_register_driver()
points to an unpaged address since the callback function will be called
from an interrup

core: notif: assert callback is unpaged

Add an assert that the atomic_cb() pointer in notif_register_driver()
points to an unpaged address since the callback function will be called
from an interrupt handler and must not be paged.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: callout: assert callback is unpaged

Add an assert that the callback parameter passed to callout_add() points
to an unpaged address since the callback function will be called from an
interrupt

core: callout: assert callback is unpaged

Add an assert that the callback parameter passed to callout_add() points
to an unpaged address since the callback function will be called from an
interrupt handler and must not be paged.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add missing DECLARE_KEEP_PAGER()

Adds missing DECLARE_KEEP_PAGER() for timer_desc, timer_itr_cb(),
arm_cntpct_time_source, wd_ndrv_atomic_cb(), and periodic_callback().
All possibly accessed f

core: add missing DECLARE_KEEP_PAGER()

Adds missing DECLARE_KEEP_PAGER() for timer_desc, timer_itr_cb(),
arm_cntpct_time_source, wd_ndrv_atomic_cb(), and periodic_callback().
All possibly accessed from an interrupt handler and must not be paged.

Fixes: cf707bd0d695 ("core: add callout service")
Fixes: 5b7afacfba96 ("core: arm64: implement timer_init_callout_service()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-synquacer: use cpu_spin_lock_xsave() and friend

Change RNG PTA implementation for synquacer platform to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead
of call

plat-synquacer: use cpu_spin_lock_xsave() and friend

Change RNG PTA implementation for synquacer platform to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead
of calling thread_mask_exceptions()/cpu_spin_lock() pair and
thread_set_exceptions()/cpu_spin_unlock() pair. This makes the
implementation more consistent.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: mm: use thread_unmask_exceptions() where applicable

Change cache_op_outer() to use thread_unmask_exceptions() instead
of thread_set_exceptions() as the function unmasks interruptions it
p

core: arm: mm: use thread_unmask_exceptions() where applicable

Change cache_op_outer() to use thread_unmask_exceptions() instead
of thread_set_exceptions() as the function unmasks interruptions it
previously masked with thread_set_exceptions(). This change makes the
implementation more consistent.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: use cpu_spin_lock_xsave() in generic timer implementation

Change generic timer driver for Arm 64bit architecture to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore

core: arm: use cpu_spin_lock_xsave() in generic timer implementation

Change generic timer driver for Arm 64bit architecture to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore()
instead of calling thread_mask_exceptions()/cpu_spin_lock() pair
and thread_set_exceptions()/cpu_spin_unlock() pair. This makes
the implementation more consistent with the rest of the source tree.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: notif_send_async(): remove debug print

Remove the debug print
D/TC:0 notif_send_async:93 0x0
from notif_send_async().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: notif_send_async(): remove debug print

Remove the debug print
D/TC:0 notif_send_async:93 0x0
from notif_send_async().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: tests: add a notification test watchdog

Add test watchdog for asynchronous notifications where a timer interrupt
triggers an asynchronous notification in the normal world kernel driver.
The no

core: tests: add a notification test watchdog

Add test watchdog for asynchronous notifications where a timer interrupt
triggers an asynchronous notification in the normal world kernel driver.
The normal world kernel driver responds by doing a
OPTEE_MSG_CMD_DO_BOTTOM_HALF call for bottom half processing. The
watchdog checks that there has been a response for each timer interrupt but
doesn't take any measures if a response is missing.

The purpose of the test is to exercise asynchronous notifications.
Feedback is limited to debug prints on the UART so eventual regressions
will not get caught by xtest unless there is a crash.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome

plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service usi

plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service using that interrupt ID.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: implement timer_init_callout_service()

Implement timer_init_callout_service() needed to initialize and drive
the callout service. Only available in AArch64.

Signed-off-by: Jens Wikland

core: arm64: implement timer_init_callout_service()

Implement timer_init_callout_service() needed to initialize and drive
the callout service. Only available in AArch64.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: define generic callout service initializer

Add a generic timer_init_callout_service() to be implemented in
architecture or platform specific code. The function shall provide an
implementation

core: define generic callout service initializer

Add a generic timer_init_callout_service() to be implemented in
architecture or platform specific code. The function shall provide an
implementation of the abstract timer interface needed by the callout
service and register a timer interrupt callback to call
callout_service_cb().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add callout service

Add a callout service to call registered callback functions at a given
time from now. A callout is periodic or oneshot depending on how the
callback function returns. Callb

core: add callout service

Add a callout service to call registered callback functions at a given
time from now. A callout is periodic or oneshot depending on how the
callback function returns. Callback functions execute in nexus and
interrupt context.

The callout service is initialized with callout_service_init() and
depends on an abstract timer interface to manage the hardware timer.
callout_service_cb() needs to be called from the timer interrupt handler
to drive the callout service.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: add {read,write}_cntps_cval()

Add read_cntps_cval() and write_cntps_cval() to access CNTPS_CVAL_EL1,
Counter-timer Physical Secure Timer CompareValue register.

Signed-off-by: Jens Wikl

core: arm64: add {read,write}_cntps_cval()

Add read_cntps_cval() and write_cntps_cval() to access CNTPS_CVAL_EL1,
Counter-timer Physical Secure Timer CompareValue register.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: clk-stm32mp13: fix memory corruption on oscillator parent

Fix oscillators struct clk instances for STM32MP13 clock driver. These
clocks have 1 parent that is set during driver initiali

drivers: clk: clk-stm32mp13: fix memory corruption on oscillator parent

Fix oscillators struct clk instances for STM32MP13 clock driver. These
clocks have 1 parent that is set during driver initialization, based on
device tree content, whereas referred bugged commit defined 0 parents
and did not allocate memory for the parent reference.

Fixes: 95f2142bf848 ("drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired")
Tested-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-synquacer: add initialization value to local variables

Add missing initialization value to local variables in synquacer
platform RNG driver to better comply with OP-TEE OS coding style
and prev

plat-synquacer: add initialization value to local variables

Add missing initialization value to local variables in synquacer
platform RNG driver to better comply with OP-TEE OS coding style
and prevent developers from being confused when using this example
as a example.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator leve

drivers: regulator: do not cache voltage level value

Always read current voltage level from the device instead of
caching the level in struct regulator. This fixes issues for
when the regulator level value depends on the parent regulator
(supply). It is up the regulator drivers to cache or not this
value in their private data if applicable.

Fixes: 1a3d3273040b ("drivers: regulator framework")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add __must_check attribute to cpu_spin_lock_xsave()

cpu_spin_lock_xsave() masks exceptions, takes the spinlock and returns
previous exception state to be restored by cpu_spin_unlock_xrestore()

core: add __must_check attribute to cpu_spin_lock_xsave()

cpu_spin_lock_xsave() masks exceptions, takes the spinlock and returns
previous exception state to be restored by cpu_spin_unlock_xrestore().
The previously returned exception state must always be supplied so add
the __must_check attribute to cpu_spin_lock_xsave() and its debug
variants.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: kernel: add timeout_elapsed_us()

Add API function timeout_elapsed_us() to measure to time since or until
an initialized timeout reference elapses.

This function relies on other timeout_*() AP

core: kernel: add timeout_elapsed_us()

Add API function timeout_elapsed_us() to measure to time since or until
an initialized timeout reference elapses.

This function relies on other timeout_*() API functions are therefore
depends on CFG_CORE_HAS_GENERIC_TIMER being enabled.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architec

core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architecture or platform only need to implement timer tick count
read function delay_cnt_read() and timer tick frequency (in Hertz)
delay_cnt_freq() which is related to CFG_CORE_HAS_GENERIC_TIMER support.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMER

Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture
since the current implementation provides the necessary routines
in delay

core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMER

Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture
since the current implementation provides the necessary routines
in delay_arch.h outside any configuration switch directive. This change
clarifies riscv based platforms configuration that previously depended
on CFG_CORE_HAS_GENERIC_TIMER default enabling from mk/config.mk.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: describe udelay()/mdelay()

Add inline description comment for udelay() and mdelay() for
consistency of OP-TEE OS source tree, even if the function names
are quite explicit and do not s

core: kernel: describe udelay()/mdelay()

Add inline description comment for udelay() and mdelay() for
consistency of OP-TEE OS source tree, even if the function names
are quite explicit and do not strictly need such descriptions.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/m

plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/main.c
doesn't make sense and needs to be disabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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