core: asan: mark redzones as inaccessible for globals

For read-only globals (e.g. in .rodata), ASan marks the entire region as
accessible. This could hide buffer overflows, if redzones are not used.

core: asan: mark redzones as inaccessible for globals

For read-only globals (e.g. in .rodata), ASan marks the entire region as
accessible. This could hide buffer overflows, if redzones are not used.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add ASan test for read-only global overflow

Adds a test case that triggers an out-of-bounds read on a read-only
global buffer to verify that ASan properly detects overflows on .rodata.

Signed

core: add ASan test for read-only global overflow

Adds a test case that triggers an out-of-bounds read on a read-only
global buffer to verify that ASan properly detects overflows on .rodata.

Signed-off-by: Aleksandr Iashchenko <aleksandr.iashchenko@linutronix.de>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Add TRNG driver support in AM62L

AM62L contains the EIP76D TRNG IP which was also present in the previous
K3 devices inside the SA2UL accelerator, so the same driver is being
re-us

plat-k3: drivers: Add TRNG driver support in AM62L

AM62L contains the EIP76D TRNG IP which was also present in the previous
K3 devices inside the SA2UL accelerator, so the same driver is being
re-used here. But the AM62L does not have SA2UL. The SoC specific
configurations are being set here for AM62L for enabling TRNG.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Move RNG platform error from SA2UL to RNG defines

The error define for RNG base address being not defined for a platform
when software PRNG is disabled, is currently handled as a c

plat-k3: drivers: Move RNG platform error from SA2UL to RNG defines

The error define for RNG base address being not defined for a platform
when software PRNG is disabled, is currently handled as a case with
SA2UL platform config definitions. This is not appropriate as RNG is not
needed to be tied up to SA2UL. Moving it to be placed with RNG platform
configs where it is more apt.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-k3: drivers: Refactor SA2UL driver

The EIP76D TRNG IP being used in current K3 devices is not unique to
SA2UL/SA3UL. The RNG driver can be reused in other devices containing
the same TRNG IP ou

plat-k3: drivers: Refactor SA2UL driver

The EIP76D TRNG IP being used in current K3 devices is not unique to
SA2UL/SA3UL. The RNG driver can be reused in other devices containing
the same TRNG IP outside of SA2UL/SA3UL.

Refactor the SA2UL and RNG driver to make EIP76D TRNG driver independent
of SA2UL.

Signed-off-by: T Pratham <t-pratham@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration t

plat-vexpress: qemu-v8: fix CFG_CORE_CLUSTER_SHIFT

QEMU virt puts 8 or 16 CPUs in each cluster, depending on the GIC
configuration [1]. So set CFG_CORE_CLUSTER_SHIFT to match the GIC
configuration to calculate core position correctly for more than 16
CPUs.

Link: https://gitlab.com/qemu-project/qemu/-/blob/v10.0.0/hw/arm/virt.c?ref_type=tags#L1785-1789 [1]
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)

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dts: stm32: add stm32mp257f-dk board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LV

dts: stm32: add stm32mp257f-dk board support

Add STM32MP257F Discovery board support. It embeds a STM32MP257FAL SoC,
with 2GB of LPDDR4, 2*USB typeA, 1*USB3 typeC, 1*ETH, wifi/BT combo,
DSI HDMI, LVDS connector ...

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: conf: add stm32mp257f-dk board support

Add support for the stm32mp257f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thom

plat-stm32mp2: conf: add stm32mp257f-dk board support

Add support for the stm32mp257f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: drivers: allow to configure RIF for GPIO not on the SoC package

The number of GPIO physically accessible depends on package.
Some GPIO pins might not be accessible but it is still possible to

core: drivers: allow to configure RIF for GPIO not on the SoC package

The number of GPIO physically accessible depends on package.
Some GPIO pins might not be accessible but it is still possible to write
RIF registers to block access.

The assert(nb_rif_conf <= bank->ngpios) mandate to have less or the same
number of RIF configuration than the number of GPIO pin describe with
the property gpio-ranges to have the same number.

Remove the assert and replace() it with MIN() to be less restrictive.

Fixes: bd03c8c3d70f ("drivers: stm32_gpio: add stm32mp25x support")
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Gof

plat-stm32mp2: enable watchdog SMC service

Enable Arm watchdog SMC service using function ID 0xbc000000.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le G

plat-stm32mp2: conf: default enable CFG_STM32_IWDG

Default enable STM32 IWDG driver on STM32MP2 platforms.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevall

dts: stm32: enable IWDG1 on stm32mp215f-dk board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.cheval

dts: stm32: enable IWDG1 on stm32mp257f-ev1 board

Enable IWDG1 node and set a 32s timeout.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gat

dts: stm32: add IWDG[1-2] nodes in stm32mp21x soc device-tree

Add support for IWDG[1-2] in stm32mp21x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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dts: stm32: add IWDG[1-2] nodes in stm32mp25x soc device-tree

Add support for IWDG[1-2] in stm32mp25x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gat

dts: stm32: add IWDG[1-2] nodes in stm32mp25x soc device-tree

Add support for IWDG[1-2] in stm32mp25x soc device-trees.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: move setup function in probe

Setup and probe are meaning mostly the same. Moving the `setup` function
content in probe improves readability.

Signed-off-by: Clément Le Goffic <c

drivers: stm32_iwdg: move setup function in probe

Setup and probe are meaning mostly the same. Moving the `setup` function
content in probe improves readability.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: change prescaler value to 1024

Increase the prescaler value to 1024 in order to increase watchdog
timeout value.
((2^12) * 1024) / 32767 = 128
It will allow watchdog timeout up

drivers: stm32_iwdg: change prescaler value to 1024

Increase the prescaler value to 1024 in order to increase watchdog
timeout value.
((2^12) * 1024) / 32767 = 128
It will allow watchdog timeout up to 128s.
Also multiply the IWDG_TIMEOUT_US by 4, same as the prescaler value.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: reload for stopped watchdog

For stopped watchdog, use the early interruption to reload the watchdog
without panic, the driver uses ULONG_MAX as an infinite reload indication.

S

drivers: stm32_iwdg: reload for stopped watchdog

For stopped watchdog, use the early interruption to reload the watchdog
without panic, the driver uses ULONG_MAX as an infinite reload indication.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: add support for extended watchdog timeout

This commit enhances the STM32 IWDG driver to support extended watchdog
timeouts.
It introduces new fields in the `stm32_iwdg_device` s

drivers: stm32_iwdg: add support for extended watchdog timeout

This commit enhances the STM32 IWDG driver to support extended watchdog
timeouts.
It introduces new fields in the `stm32_iwdg_device` structure, updates
the interrupt handler to handle multiple refresh cycles, and improves
the timeout handling logic to manage and calculate extended timeouts
accurately.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: add stop watchdog handler

Implement .stop watchdog handler in order to allow the platform to
`halt` well.

The platform does not allow a way to stop an IWDG once started but a
s

drivers: stm32_iwdg: add stop watchdog handler

Implement .stop watchdog handler in order to allow the platform to
`halt` well.

The platform does not allow a way to stop an IWDG once started but a
solution exists.
We disable the platform reset ability of the IWDG we use and the IRQ
associated if the reset property is present in the DT.

Be careful, on STM32MP2 platforms, in A35TDCID, the system reset of the
IWDG1 cannot be disabled. Therefore, only the IWDG2 can be stopped.
The same behavior applies for IWDG3 in M33TDCID, you'll have to use the
IWDG4.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: disable clocks during PM standby

Disable STM32 IWDG clock during low power state.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffi

drivers: stm32_iwdg: disable clocks during PM standby

Disable STM32 IWDG clock during low power state.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: early watchdog interrupt

When the secure device tree defines an interrupt, register a handler
to notify secure world of a possible watchdog expiration.

Signed-off-by: Etienne C

drivers: stm32_iwdg: early watchdog interrupt

When the secure device tree defines an interrupt, register a handler
to notify secure world of a possible watchdog expiration.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: maintain the panicked TAs with instanceKeepCrashed property

TA context lists should retain panicked TAs (those with the
TA_FLAG_SINGLE_INSTANCE, TA_FLAG_INSTANCE_KEEP_ALIVE, and
TA_FLAG_INSTAN

core: maintain the panicked TAs with instanceKeepCrashed property

TA context lists should retain panicked TAs (those with the
TA_FLAG_SINGLE_INSTANCE, TA_FLAG_INSTANCE_KEEP_ALIVE, and
TA_FLAG_INSTANCE_KEEP_CRASHED flags) to maintain their panicked state and
prevent respawning.

Fixes: 941a58d78c99 ("Add optee.ta.instanceKeepCrashed property")
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-versal2: use auto PA bit discovery

Removes hardcoded configuration for large physical address and
ARM64 PA bits, enabling automatic discovery of the maximal PA
supported by the hardware.

Signe

plat-versal2: use auto PA bit discovery

Removes hardcoded configuration for large physical address and
ARM64 PA bits, enabling automatic discovery of the maximal PA
supported by the hardware.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized sta

plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized status and control (SSC) registers

This path removes the confusion between SSC and subsystem (SS).

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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