core: add memory area for transfer list

Adding a new area to map a transfer list if it is handed over
from previous boot stage

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Jens

core: add memory area for transfer list

Adding a new area to map a transfer list if it is handed over
from previous boot stage

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove unused mobj_mm_alloc()

Removes the now unused mobj_mm_alloc(), struct mobj_mm, and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienn

core: remove unused mobj_mm_alloc()

Removes the now unused mobj_mm_alloc(), struct mobj_mm, and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove deprecated vm_add_rwmem() and vm_rem_rwmem()

Removes the two deprecated and now also unused functions vm_add_rwmem()
and vm_rem_rwmem().

Signed-off-by: Jens Wiklander <jens.wiklander@l

core: remove deprecated vm_add_rwmem() and vm_rem_rwmem()

Removes the two deprecated and now also unused functions vm_add_rwmem()
and vm_rem_rwmem().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove unused mobj_seccpy_shm_alloc()

Removes the now unused mobj_seccpy_shm_alloc(), struct mobj_seccpy_shm,
and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by:

core: remove unused mobj_seccpy_shm_alloc()

Removes the now unused mobj_seccpy_shm_alloc(), struct mobj_seccpy_shm,
and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: SPMC obtain device memory info from DTB

When CFG_CORE_SEL2_SPMC = y, obtain device memory info from
the SP manifest DTB.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wikland

core: arm: SPMC obtain device memory info from DTB

When CFG_CORE_SEL2_SPMC = y, obtain device memory info from
the SP manifest DTB.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: make core_mmu_set_secure_memory() available

Makes core_mmu_set_secure_memory() unconditionally available, but add a
runtime_assert() to protect against calls without
CFG_CORE_PHYS_RELOCATABLE=

core: make core_mmu_set_secure_memory() available

Makes core_mmu_set_secure_memory() unconditionally available, but add a
runtime_assert() to protect against calls without
CFG_CORE_PHYS_RELOCATABLE=y.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add MEM_AREA_MANIFEST_DT

Adds MEM_AREA_MANIFEST_DT for mapping an FF-A manifest FDT.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by:

core: add MEM_AREA_MANIFEST_DT

Adds MEM_AREA_MANIFEST_DT for mapping an FF-A manifest FDT.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: vm_info_final(): clear vm_info.asid only

vm_info_final() was prior to this patch clearing the entire
uctx->vm_info when clearing uctx->vm_info.asid only is enough. So fix
that by clearing uctx

core: vm_info_final(): clear vm_info.asid only

vm_info_final() was prior to this patch clearing the entire
uctx->vm_info when clearing uctx->vm_info.asid only is enough. So fix
that by clearing uctx->vm_info.asid only.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: move pgt_cache.c to core/mm

This commit moves core/arch/arm/mm/pgt_cache.c to core/mm/pgt_cache.c
The implementation can be used by other architectures.
The commit does not rename CFG_CORE

core: mm: move pgt_cache.c to core/mm

This commit moves core/arch/arm/mm/pgt_cache.c to core/mm/pgt_cache.c
The implementation can be used by other architectures.
The commit does not rename CFG_CORE_PREALLOC_EL0_TBLS flag and other
depending flags (CFG_WITH_PAGER, CFG_WITH_LPAE). Therefore, an
architecture implementation may set or not these flags.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: mm: Fix conflicting types due to enum/integer mismatch

This is an error with gcc13 [-Werror=enum-int-mismatch]

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jose Quar

core: mm: Fix conflicting types due to enum/integer mismatch

This is an error with gcc13 [-Werror=enum-int-mismatch]

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jose Quaresma <jose.quaresma@foundries.io>

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core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename

core: mm: Rename "mva" to "va" for TLB operations

The terminology "mva" is specific for older ARM architecture which has
FCSE extension. To support multiple architecture, it would be good to
rename "mva" to common terminology, such as "va". This PR renames "mva"
to "va" in TLB operations for ARM64 and RISC-V. For ARM32, "mva" is
reserved because it is really defined in ARM32's documentations.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: mm: Introduce next_level field of struct core_mmu_table_info

The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-g

core: mm: Introduce next_level field of struct core_mmu_table_info

The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-grained table,
while RISC-V adopts decreasing style. Therefore, we add a "next_level"
field into the struct core_mmu_table_info, which represents the next
finer-grained translation level. By doing this, we can decouple the
core address translation rule from architecture specific manner.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: Introduce core_mmu_level_in_range()

Since the checking of the valid translation level is architecture
specific, the core_mmu_level_in_range() is introduced and every
architecture could imp

core: mm: Introduce core_mmu_level_in_range()

Since the checking of the valid translation level is architecture
specific, the core_mmu_level_in_range() is introduced and every
architecture could implement the function with their own translation
rules.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add memory type MEM_AREA_NEX_NSEC_SHM

Adds the memory type MEM_AREA_NEX_NSEC_SHM used to map non-secure shared
memory in the nexus.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: add memory type MEM_AREA_NEX_NSEC_SHM

Adds the memory type MEM_AREA_NEX_NSEC_SHM used to map non-secure shared
memory in the nexus.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link ad

core: support physically relocatable OP-TEE binary

With CFG_CORE_PHYS_RELOCATABLE=y enable support in OP-TEE to relocate
itself to allow it to run from physical address that differs from the
link address.

This feature is currently only supported with CFG_CORE_SEL2_SPMC=y since
the TEE core has to know the range of available memory. With SPMC at EL2
this is accomplished via get_sec_mem_from_manifest(). An SPMC at S-EL2
may need to load OP-TEE at a different address depending on
configuration.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_set_secure_memory()

Adds core_mmu_set_secure_memory() for use with CFG_CORE_PHYS_RELOCATABLE
where the secure physical memory range is determined at boot.

Reviewed-by: Etienne Ca

core: add core_mmu_set_secure_memory()

Adds core_mmu_set_secure_memory() for use with CFG_CORE_PHYS_RELOCATABLE
where the secure physical memory range is determined at boot.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu.c: only try to add pager vaspace when enabled

Only call add_pager_vaspace() when compiled with pager enabled to avoid
redundant looping over the memory areas to map.

Reviewed-by: Eti

core: core_mmu.c: only try to add pager vaspace when enabled

Only call add_pager_vaspace() when compiled with pager enabled to avoid
redundant looping over the memory areas to map.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu.c: use secure_only[] where possible

Avoid using TEE_RAM_START, TEE_RAM_PH_SIZE, TA_RAM_START, and
TA_RAM_SIZE where secure_only[] can be used instead to calculate the
same numbers.

R

core: core_mmu.c: use secure_only[] where possible

Avoid using TEE_RAM_START, TEE_RAM_PH_SIZE, TA_RAM_START, and
TA_RAM_SIZE where secure_only[] can be used instead to calculate the
same numbers.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_get_ta_range()

Adds core_mmu_get_ta_range() to return the range of physical memory
reserved for TAs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Je

core: add core_mmu_get_ta_range()

Adds core_mmu_get_ta_range() to return the range of physical memory
reserved for TAs.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_tee_load_pa address

Adds core_mmu_tee_load_pa for a dynamic record of where OP-TEE is loaded
into memory.

With CFG_CORE_PHYS_RELOCATABLE=y core_mmu_tee_base_pa may need to be
upd

core: add core_mmu_tee_load_pa address

Adds core_mmu_tee_load_pa for a dynamic record of where OP-TEE is loaded
into memory.

With CFG_CORE_PHYS_RELOCATABLE=y core_mmu_tee_base_pa may need to be
updated during early boot since the physical address to use isn't
determined until then.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_get_secure_memory()

Adds core_mmu_get_secure_memory() with the primary purpose of being used
to find out the memory range to pass to memtag_set_tags().

Signed-off-by: Jens Wiklan

core: add core_mmu_get_secure_memory()

Adds core_mmu_get_secure_memory() with the primary purpose of being used
to find out the memory range to pass to memtag_set_tags().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: pass secure memory parameter to virt_init_memory()

Pass the physical secure memory range as a parameter from secure_only[].
This avoids using hard coded defines in virt_init_memory().

CFG_NS_

core: pass secure memory parameter to virt_init_memory()

Pass the physical secure memory range as a parameter from secure_only[].
This avoids using hard coded defines in virt_init_memory().

CFG_NS_VIRTUALIZATION=y depends on secure_only[] to have all memory as
consecutive memory ranges, but that's unchanged behaviour from before
since it was expected that the entire range from TEE_RAM_START to
TA_RAM_START + TA_RAM_SIZE is usable memory.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: core_mmu.c: use boot_mmu_config.map_offset

Use boot_mmu_config.map_offset instead of computing it with
VCORE_START_VA and TEE_LOAD_ADDR.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.o

core: core_mmu.c: use boot_mmu_config.map_offset

Use boot_mmu_config.map_offset instead of computing it with
VCORE_START_VA and TEE_LOAD_ADDR.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: rename load_offset in struct core_mmu_config

Renames the field load_offset in struct core_mmu_config to the more
accurate name map_offset.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro

core: rename load_offset in struct core_mmu_config

Renames the field load_offset in struct core_mmu_config to the more
accurate name map_offset.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: core_mmu.c: replace register_phys_mem{_ul,}() usage

Replaces register_phys_mem_ul() and register_phys_mem() with direct
calls to ADD_PHYS_MEM() for core and TA memory. This makes the code
easi

core: core_mmu.c: replace register_phys_mem{_ul,}() usage

Replaces register_phys_mem_ul() and register_phys_mem() with direct
calls to ADD_PHYS_MEM() for core and TA memory. This makes the code
easier to read and also gives better control over supplied addresses
since static initialization can be avoided.

This patch has no functional change.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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