core: improve register_phys_mem_pgdir() debug print

Improves the debug prints emitted by register_phys_mem_pgdir() to use
the define of the base address instead. For example:
ROUNDDOWN(0x09040000, C

core: improve register_phys_mem_pgdir() debug print

Improves the debug prints emitted by register_phys_mem_pgdir() to use
the define of the base address instead. For example:
ROUNDDOWN(0x09040000, CORE_MMU_PGDIR_SIZE) type IO_SEC 0x09000000 size 0x00200000
becomes:
CONSOLE_UART_BASE type IO_SEC 0x09000000 size 0x00200000

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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virt: rename CFG_VIRTUALIZATION to CFG_NS_VIRTUALIZATION

With the advent of virtualization support at S-EL2 in the Armv8.4-A
architecture, CFG_VIRTUALIZATION has become ambiguous. Let's rename
it to

virt: rename CFG_VIRTUALIZATION to CFG_NS_VIRTUALIZATION

With the advent of virtualization support at S-EL2 in the Armv8.4-A
architecture, CFG_VIRTUALIZATION has become ambiguous. Let's rename
it to CFG_NS_VIRTUALIZATION to indicate more clearly that it is about
supporting virtualization on the non-secure side.

This commit is the result of the following command:

$ for f in $(git grep -l -w CFG_VIRTUALIZATION); do \
sed -i -e 's/CFG_VIRTUALIZATION/CFG_NS_VIRTUALIZATION/g' $f; \
done

...plus the compatibility line in mk/config.mk:

CFG_NS_VIRTUALIZATION ?= $(CFG_VIRTUALIZATION)

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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core: simplify pgt interface provided by pgt_cache.h

Many of the function in the pgt interface takes more than one pointer to
struct pgt_cache, struct vm_info or struct ts_ctx. All these pointers
ar

core: simplify pgt interface provided by pgt_cache.h

Many of the function in the pgt interface takes more than one pointer to
struct pgt_cache, struct vm_info or struct ts_ctx. All these pointers
are available in struct user_mode_ctx so pass a pointer to that struct
instead. This saves a few function arguments and also makes it a bit
more clear how a function can be used.

pgt_clear_ctx_range(), pgt_flush_ctx_range() and pgt_flush_ctx() are
renamed to drop the "_ctx" part in their names since it's not relevant
any longer.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pgt: support preallocated translation tables for S-EL0

With CFG_CORE_PREALLOC_EL0_TBLS=y translation tables are allocated for a
user space context at the time when the mapping is added a struc

core: pgt: support preallocated translation tables for S-EL0

With CFG_CORE_PREALLOC_EL0_TBLS=y translation tables are allocated for a
user space context at the time when the mapping is added a struct
vm_region. The translation tables will be kept available for the S-EL0
context as long at the mappings are unchanged.

Secure Partitions (SPs) can depend on translation tables always being
available and avoid having to wait for translation tables.

Memory for the translation tables is allocated from the same memory as
used for TAs and SPs. The number of available translation tables are
limited by the amount of TA/SP memory available.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pgt: rename to pgt_put_all() and pgt_get_all()

The two functions pgt_free() and pgt_alloc() has names which doesn't
match well what they do so rename them.

pgt_free() to pgt_put_all():
This m

core: pgt: rename to pgt_put_all() and pgt_get_all()

The two functions pgt_free() and pgt_alloc() has names which doesn't
match well what they do so rename them.

pgt_free() to pgt_put_all():
This matches better how page tables are managed since pgt_put_all()
doesn't free the tables, they are just put in a cache list from which
they later can be free or re-allocated.

pgt_alloc() to pgt_get_all():
pgt_get_all() may actually not allocate a new table, not if it can be
found in the cache list.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pgt: use pgt_cache_list without pager too

Prior to this patch was only unused pgts cached when paging was enabled.
Take this one step further and cache unused pgts when paging is disabled
too.

core: pgt: use pgt_cache_list without pager too

Prior to this patch was only unused pgts cached when paging was enabled.
Take this one step further and cache unused pgts when paging is disabled
too. The purpose of this is to allow core_mmu_populate_user_map() to
skip already initialized translation tables.

Add two helper functions pgt_pop_from_cache_list() and
pgt_push_to_cache_list() to be used when updating the translation tables
currently in the cache list.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tee_pager.h: provide stubbed tee_pager_pgt_save_and_release_entries()

Provides a stubbed static inline
tee_pager_pgt_save_and_release_entries() when CFG_PAGED_USER_TA isn't
defined.

Reviewed-

core: tee_pager.h: provide stubbed tee_pager_pgt_save_and_release_entries()

Provides a stubbed static inline
tee_pager_pgt_save_and_release_entries() when CFG_PAGED_USER_TA isn't
defined.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: initialize struct user_mode_ctx with vm_info_init()

Broadens the scope of vm_info_init() to initialize the entire struct
user_mode_ctx.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.

core: initialize struct user_mode_ctx with vm_info_init()

Broadens the scope of vm_info_init() to initialize the entire struct
user_mode_ctx.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove save_ctx parameter from pgt_free()

Prior to this patch was pgt_free() taking a save_ctx parameter which was
only used if paging of TAs was enabled. If on the other hand paging of
TAs wa

core: remove save_ctx parameter from pgt_free()

Prior to this patch was pgt_free() taking a save_ctx parameter which was
only used if paging of TAs was enabled. If on the other hand paging of
TAs was enabled this parameter was always true. So simplify the logic by
removing this parameter and where used internally always do as if
save_ctx was true. This means that pgts used for paging will always
first be pushed to the cache list to later be reclaimed by other means.

This patch does not change the de facto behaviour.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: return true for mattr_is_cached() and TEE_MATTR_MEM_TYPE_TAGGED

Memory areas tagged with TEE_MATTR_MEM_TYPE_TAGGED attributes are
cached. Modify mattr_is_cached() accordingly.

Fixes: 7c3a

core: mm: return true for mattr_is_cached() and TEE_MATTR_MEM_TYPE_TAGGED

Memory areas tagged with TEE_MATTR_MEM_TYPE_TAGGED attributes are
cached. Modify mattr_is_cached() accordingly.

Fixes: 7c3ab7744d ("core: mm: add TEE_MATTR_MEM_TYPE_TAGGED")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: handle large holes in S-EL0 map

Prior to this patch it was assumed that the memory map of a user mode
context had no holes or very small holes. This leads to a higher pressure
on the translati

core: handle large holes in S-EL0 map

Prior to this patch it was assumed that the memory map of a user mode
context had no holes or very small holes. This leads to a higher pressure
on the translation tables than necessary.

So fix this by skipping to allocate translation tables for holes in the
memory map of a user mode context where possible.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: deprecate vm_add_rwmem() and vm_rem_rwmem()

Deprecates vm_add_rwmem() and vm_rem_rwmem(), they should only be
called from mobj_seccpy_shm_alloc() and mobj_seccpy_shm_free().

Reviewed-by: Etie

core: deprecate vm_add_rwmem() and vm_rem_rwmem()

Deprecates vm_add_rwmem() and vm_rem_rwmem(), they should only be
called from mobj_seccpy_shm_alloc() and mobj_seccpy_shm_free().

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sp_mem: fix get_cattr() callback name

Commit 8afe7a7c5220 ("core: rename mobj_get_cattr() to
mobj_get_mem_type()") renames the get_cattr() callback in struct
mobj_ops(). However, sp_mem wasn't

core: sp_mem: fix get_cattr() callback name

Commit 8afe7a7c5220 ("core: rename mobj_get_cattr() to
mobj_get_mem_type()") renames the get_cattr() callback in struct
mobj_ops(). However, sp_mem wasn't updated as part of this change, so
currently it doesn't compile. Fix this and get aligned with the new
naming.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: map TA memory using TEE_MATTR_MEM_TYPE_TAGGED

Maps TA memory using the TEE_MATTR_MEM_TYPE_TAGGED which results in
tagged cached memory if the system has it enabled.

Acked-by: Etienne Carriere

core: map TA memory using TEE_MATTR_MEM_TYPE_TAGGED

Maps TA memory using the TEE_MATTR_MEM_TYPE_TAGGED which results in
tagged cached memory if the system has it enabled.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: add TEE_MATTR_MEM_TYPE_TAGGED

Adds TEE_MATTR_MEM_TYPE_TAGGED used to map tagged memory as defined in
Armv8.5-A Memory Tagging Extension (MTE).

All OP-TEE core memory should be mapped as t

core: mm: add TEE_MATTR_MEM_TYPE_TAGGED

Adds TEE_MATTR_MEM_TYPE_TAGGED used to map tagged memory as defined in
Armv8.5-A Memory Tagging Extension (MTE).

All OP-TEE core memory should be mapped as tagged memory when supported.

Memory potentially shared with non-secure world or other firmware should
not be mapped as tagged since we don't have control over the tags then.

The mappings used by TEE_MATTR_MEM_TYPE_TAGGED is replaced by
TEE_MATTR_MEM_TYPE_CACHED if MTE isn't supported or configured.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: recognize tag check faults in abort handler

Adds support in the abort handler to recognize tag check faults.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carr

core: recognize tag check faults in abort handler

Adds support in the abort handler to recognize tag check faults.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename mobj_get_cattr() to mobj_get_mem_type()

Renames mobj_get_cattr() to mobj_get_mem_type(). The mobj operation
get_ctype() is also renamed to get_mem_type().

This commit is only about ren

core: rename mobj_get_cattr() to mobj_get_mem_type()

Renames mobj_get_cattr() to mobj_get_mem_type(). The mobj operation
get_ctype() is also renamed to get_mem_type().

This commit is only about renaming ctype to mem_type, no changes in
behaviour.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: fix core virtual address range constraint in lpae

Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
con

core: mm: fix core virtual address range constraint in lpae

Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
configuration the virtual memory addresses are expected to fit in a
single base translation table in order to save 4kB translation pages.
This change makes core to fallback to the generic layout, possibly
spreading virtual addresses over several base translation tables if
the virtual memory addresses do not fit in the optimized address
range preferred for that configuration.

Fixes: https://github.com/OP-TEE/optee_os/issues/5201
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: sp_mem: add security attribute

Currently sp_mem only supports non-secure memory. This patch enables
using it for secure memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed

core: sp_mem: add security attribute

Currently sp_mem only supports non-secure memory. This patch enables
using it for secure memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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core: sp_mem: add memory type attribute

Currently sp_mem only supports TEE_MATTR_MEM_TYPE_CACHE memory type.
This patch adds support for using it with any type so it can be used
for device memory to

core: sp_mem: add memory type attribute

Currently sp_mem only supports TEE_MATTR_MEM_TYPE_CACHE memory type.
This patch adds support for using it with any type so it can be used
for device memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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core: provide dummy mobj_reg_shm_get_by_cookie()

Provides a dummy static inlined mobj_reg_shm_get_by_cookie() returning NULL
in case CFG_CORE_DYN_SHM=n.

Reviewed-by: Jerome Forissier <jerome@foriss

core: provide dummy mobj_reg_shm_get_by_cookie()

Provides a dummy static inlined mobj_reg_shm_get_by_cookie() returning NULL
in case CFG_CORE_DYN_SHM=n.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add support for DEVICE_nGnRnE

Currently OP-TEE only allows non-cached memory to be mapped as
ATTR_DEVICE_nGnRE/Device. This patch adds support for
ATTR_DEVICE_nGnRnE/Strongly-ordered.

Signed-

core: Add support for DEVICE_nGnRnE

Currently OP-TEE only allows non-cached memory to be mapped as
ATTR_DEVICE_nGnRE/Device. This patch adds support for
ATTR_DEVICE_nGnRnE/Strongly-ordered.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: Add mattr_is_cached()

mattr_is_cached() can be used to determine if the mattr is cached or
not.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@lina

core: Add mattr_is_cached()

mattr_is_cached() can be used to determine if the mattr is cached or
not.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: change TEE_MATTR_CACHE_ to TEE_MATTR_MEM_TYPE_

Some extra memory types will be added. This patch renames all
TEE_MATTR_CACHE_ defines to TEE_MATTR_MEM_TYPE_. This will make the next
patches ea

core: change TEE_MATTR_CACHE_ to TEE_MATTR_MEM_TYPE_

Some extra memory types will be added. This patch renames all
TEE_MATTR_CACHE_ defines to TEE_MATTR_MEM_TYPE_. This will make the next
patches easier to understand.

Signed-off-by: Jelle Sels <jelle.sels@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: split core/arch/arm/mm/core_mmu.c

Splits core/arch/arm/mm/core_mmu.c into one generic and one architecture
specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene

core: split core/arch/arm/mm/core_mmu.c

Splits core/arch/arm/mm/core_mmu.c into one generic and one architecture
specific file.

Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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