1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 * Copyright (c) 2016-2018, Linaro Limited 5 */ 6 7 #include <boot_api.h> 8 #include <config.h> 9 #include <console.h> 10 #include <drivers/gic.h> 11 #include <drivers/stm32_etzpc.h> 12 #include <drivers/stm32mp1_etzpc.h> 13 #include <drivers/stm32_tamp.h> 14 #include <drivers/stm32_uart.h> 15 #include <dt-bindings/clock/stm32mp1-clks.h> 16 #include <kernel/boot.h> 17 #include <kernel/dt.h> 18 #include <kernel/interrupt.h> 19 #include <kernel/misc.h> 20 #include <kernel/panic.h> 21 #include <kernel/spinlock.h> 22 #include <mm/core_memprot.h> 23 #include <platform_config.h> 24 #include <sm/psci.h> 25 #include <stm32_util.h> 26 #include <trace.h> 27 28 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE); 29 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE); 30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE); 31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE); 32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE); 33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE); 34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE); 35 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB3_BASE, APB4_SIZE); 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, APB5_BASE, APB5_SIZE); 38 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB4_BASE, AHB4_SIZE); 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AHB5_BASE, AHB5_SIZE); 40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, GIC_SIZE); 41 42 register_ddr(DDR_BASE, CFG_DRAM_SIZE); 43 44 #define _ID2STR(id) (#id) 45 #define ID2STR(id) _ID2STR(id) 46 47 static TEE_Result platform_banner(void) 48 { 49 #ifdef CFG_EMBED_DTB 50 IMSG("Platform stm32mp1: flavor %s - DT %s", 51 ID2STR(PLATFORM_FLAVOR), 52 ID2STR(CFG_EMBED_DTB_SOURCE_FILE)); 53 #else 54 IMSG("Platform stm32mp1: flavor %s - no device tree", 55 ID2STR(PLATFORM_FLAVOR)); 56 #endif 57 58 return TEE_SUCCESS; 59 } 60 service_init(platform_banner); 61 62 /* 63 * Console 64 * 65 * CFG_STM32_EARLY_CONSOLE_UART specifies the ID of the UART used for 66 * trace console. Value 0 disables the early console. 67 * 68 * We cannot use the generic serial_console support since probing 69 * the console requires the platform clock driver to be already 70 * up and ready which is done only once service_init are completed. 71 */ 72 static struct stm32_uart_pdata console_data; 73 74 void console_init(void) 75 { 76 /* Early console initialization before MMU setup */ 77 struct uart { 78 paddr_t pa; 79 bool secure; 80 } uarts[] = { 81 [0] = { .pa = 0 }, 82 [1] = { .pa = USART1_BASE, .secure = true, }, 83 [2] = { .pa = USART2_BASE, .secure = false, }, 84 [3] = { .pa = USART3_BASE, .secure = false, }, 85 [4] = { .pa = UART4_BASE, .secure = false, }, 86 [5] = { .pa = UART5_BASE, .secure = false, }, 87 [6] = { .pa = USART6_BASE, .secure = false, }, 88 [7] = { .pa = UART7_BASE, .secure = false, }, 89 [8] = { .pa = UART8_BASE, .secure = false, }, 90 }; 91 92 COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); 93 94 if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) 95 return; 96 97 /* No clock yet bound to the UART console */ 98 console_data.clock = NULL; 99 100 console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; 101 stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); 102 103 register_serial_console(&console_data.chip); 104 105 IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); 106 } 107 108 #ifdef CFG_EMBED_DTB 109 static TEE_Result init_console_from_dt(void) 110 { 111 struct stm32_uart_pdata *pd = NULL; 112 void *fdt = NULL; 113 int node = 0; 114 TEE_Result res = TEE_ERROR_GENERIC; 115 116 fdt = get_embedded_dt(); 117 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 118 if (res == TEE_ERROR_ITEM_NOT_FOUND) { 119 fdt = get_external_dt(); 120 res = get_console_node_from_dt(fdt, &node, NULL, NULL); 121 if (res == TEE_ERROR_ITEM_NOT_FOUND) 122 return TEE_SUCCESS; 123 if (res != TEE_SUCCESS) 124 return res; 125 } 126 127 pd = stm32_uart_init_from_dt_node(fdt, node); 128 if (!pd) { 129 IMSG("DTB disables console"); 130 register_serial_console(NULL); 131 return TEE_SUCCESS; 132 } 133 134 /* Replace early console with the new one */ 135 console_flush(); 136 console_data = *pd; 137 free(pd); 138 register_serial_console(&console_data.chip); 139 IMSG("DTB enables console (%ssecure)", pd->secure ? "" : "non-"); 140 141 return TEE_SUCCESS; 142 } 143 144 /* Probe console from DT once clock inits (service init level) are completed */ 145 service_init_late(init_console_from_dt); 146 #endif 147 148 /* 149 * GIC init, used also for primary/secondary boot core wake completion 150 */ 151 static struct gic_data gic_data; 152 153 void itr_core_handler(void) 154 { 155 gic_it_handle(&gic_data); 156 } 157 158 void main_init_gic(void) 159 { 160 gic_init(&gic_data, GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 161 itr_init(&gic_data.chip); 162 163 stm32mp_register_online_cpu(); 164 } 165 166 void main_secondary_init_gic(void) 167 { 168 gic_cpu_init(&gic_data); 169 170 stm32mp_register_online_cpu(); 171 } 172 173 static TEE_Result init_stm32mp1_drivers(void) 174 { 175 /* Without secure DTB support, some drivers must be inited */ 176 if (!IS_ENABLED(CFG_EMBED_DTB)) 177 stm32_etzpc_init(ETZPC_BASE); 178 179 /* Secure internal memories for the platform, once ETZPC is ready */ 180 etzpc_configure_tzma(0, ETZPC_TZMA_ALL_SECURE); 181 etzpc_lock_tzma(0); 182 183 COMPILE_TIME_ASSERT(((SYSRAM_BASE + SYSRAM_SIZE) <= CFG_TZSRAM_START) || 184 ((SYSRAM_BASE <= CFG_TZSRAM_START) && 185 (SYSRAM_SEC_SIZE >= CFG_TZSRAM_SIZE))); 186 187 etzpc_configure_tzma(1, SYSRAM_SEC_SIZE >> SMALL_PAGE_SHIFT); 188 etzpc_lock_tzma(1); 189 190 return TEE_SUCCESS; 191 } 192 193 service_init_late(init_stm32mp1_drivers); 194 195 static TEE_Result init_late_stm32mp1_drivers(void) 196 { 197 TEE_Result res = TEE_ERROR_GENERIC; 198 199 /* Set access permission to TAM backup registers */ 200 if (IS_ENABLED(CFG_STM32_TAMP)) { 201 struct stm32_bkpregs_conf conf = { 202 .nb_zone1_regs = TAMP_BKP_REGISTER_ZONE1_COUNT, 203 .nb_zone2_regs = TAMP_BKP_REGISTER_ZONE2_COUNT, 204 }; 205 206 res = stm32_tamp_set_secure_bkpregs(&conf); 207 if (res == TEE_ERROR_DEFER_DRIVER_INIT) { 208 /* TAMP driver was not probed if disabled in the DT */ 209 res = TEE_SUCCESS; 210 } 211 if (res) 212 panic(); 213 } 214 215 return TEE_SUCCESS; 216 } 217 218 driver_init_late(init_late_stm32mp1_drivers); 219 220 vaddr_t stm32_rcc_base(void) 221 { 222 static struct io_pa_va base = { .pa = RCC_BASE }; 223 224 return io_pa_or_va_secure(&base, 1); 225 } 226 227 vaddr_t get_gicd_base(void) 228 { 229 struct io_pa_va base = { .pa = GIC_BASE + GICD_OFFSET }; 230 231 return io_pa_or_va_secure(&base, 1); 232 } 233 234 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg) 235 { 236 cfg->base = BSEC_BASE; 237 cfg->upper_start = STM32MP1_UPPER_OTP_START; 238 cfg->max_id = STM32MP1_OTP_MAX_ID; 239 } 240 241 bool stm32mp_is_closed_device(void) 242 { 243 uint32_t otp = 0; 244 TEE_Result result = TEE_ERROR_GENERIC; 245 246 /* Non closed_device platform expects fuse well programmed to 0 */ 247 result = stm32_bsec_shadow_read_otp(&otp, DATA0_OTP); 248 if (!result && !(otp & BIT(DATA0_OTP_SECURED_POS))) 249 return false; 250 251 return true; 252 } 253 254 bool __weak stm32mp_with_pmic(void) 255 { 256 return false; 257 } 258 259 uint32_t may_spin_lock(unsigned int *lock) 260 { 261 if (!lock || !cpu_mmu_enabled()) 262 return 0; 263 264 return cpu_spin_lock_xsave(lock); 265 } 266 267 void may_spin_unlock(unsigned int *lock, uint32_t exceptions) 268 { 269 if (!lock || !cpu_mmu_enabled()) 270 return; 271 272 cpu_spin_unlock_xrestore(lock, exceptions); 273 } 274 275 static vaddr_t stm32_tamp_base(void) 276 { 277 static struct io_pa_va base = { .pa = TAMP_BASE }; 278 279 return io_pa_or_va_secure(&base, 1); 280 } 281 282 static vaddr_t bkpreg_base(void) 283 { 284 return stm32_tamp_base() + TAMP_BKP_REGISTER_OFF; 285 } 286 287 vaddr_t stm32mp_bkpreg(unsigned int idx) 288 { 289 return bkpreg_base() + (idx * sizeof(uint32_t)); 290 } 291 292 #ifdef CFG_STM32_GPIO 293 vaddr_t stm32_get_gpio_bank_base(unsigned int bank) 294 { 295 static struct io_pa_va gpios_nsec_base = { .pa = GPIOS_NSEC_BASE }; 296 static struct io_pa_va gpioz_base = { .pa = GPIOZ_BASE }; 297 298 /* Get secure mapping address for GPIOZ */ 299 if (bank == GPIO_BANK_Z) 300 return io_pa_or_va_secure(&gpioz_base, GPIO_BANK_OFFSET); 301 302 COMPILE_TIME_ASSERT(GPIO_BANK_A == 0); 303 assert(bank <= GPIO_BANK_K); 304 305 return io_pa_or_va_nsec(&gpios_nsec_base, 306 (bank + 1) * GPIO_BANK_OFFSET) + 307 (bank * GPIO_BANK_OFFSET); 308 } 309 310 unsigned int stm32_get_gpio_bank_offset(unsigned int bank) 311 { 312 if (bank == GPIO_BANK_Z) 313 return 0; 314 315 assert(bank <= GPIO_BANK_K); 316 return bank * GPIO_BANK_OFFSET; 317 } 318 319 unsigned int stm32_get_gpio_bank_clock(unsigned int bank) 320 { 321 if (bank == GPIO_BANK_Z) 322 return GPIOZ; 323 324 assert(bank <= GPIO_BANK_K); 325 return GPIOA + bank; 326 } 327 328 #ifdef CFG_DRIVERS_CLK 329 struct clk *stm32_get_gpio_bank_clk(unsigned int bank) 330 { 331 if (bank == GPIO_BANK_Z) 332 return stm32mp_rcc_clock_id_to_clk(GPIOZ); 333 334 assert(bank <= GPIO_BANK_K); 335 return stm32mp_rcc_clock_id_to_clk(GPIOA + bank); 336 } 337 #endif 338 #endif /* CFG_STM32_GPIO */ 339