drivers: atmel_rtc: add atmel_rtc_get_tamper_timestamp()

The sama5d2 RTC actually hold the timestamp of the last tampering
attempt. Add a function to get the last time of tampering detection.

Acked

drivers: atmel_rtc: add atmel_rtc_get_tamper_timestamp()

The sama5d2 RTC actually hold the timestamp of the last tampering
attempt. Add a function to get the last time of tampering detection.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: scmi-msg: add SCMI MSG message protocol

Implements MSG header protocol to handle SCMI messages. MSG header
protocol was introduced in Linux kernel v5.15 [1]. It relies on normal
cached shar

drivers: scmi-msg: add SCMI MSG message protocol

Implements MSG header protocol to handle SCMI messages. MSG header
protocol was introduced in Linux kernel v5.15 [1]. It relies on normal
cached shared memory buffer using a 32bit header followed by the SCMI
message payload.

To support this message interface, the SCMI PTA defines a new capability
and a new command. Capability PTA_SCMI_CAPS_MSG_HEADER allows client and
service to negotiate the desired transport configuration. Command
PTA_SCMI_CMD_PROCESS_MSG_CHANNEL allows client to request processing
of a message sent based on that message exchange protocol.

Platforms shall enable configuration switch CFG_SCMI_MSG_SHM_MSG to have
their SCMI service supporting that communication protocol.

Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f301bba0ca7392d16a6ea4f1d264a91f1fadea1a
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: imx_snvs: add master key selection

Select the OTPMK as the SNVS master key when the platforms is in closed
state.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Fori

drivers: imx_snvs: add master key selection

Select the OTPMK as the SNVS master key when the platforms is in closed
state.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: drivers: merge i.MX SNVS driver files

Move the implementation of plat_rpmb_key_is_ready() from
plat-imx/drivers/imx_snvs.c to drivers/imx_snvs.c

Signed-off-by: Clement Faure <clement.faure@nx

core: drivers: merge i.MX SNVS driver files

Move the implementation of plat_rpmb_key_is_ready() from
plat-imx/drivers/imx_snvs.c to drivers/imx_snvs.c

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: scmi-msg: correct inline description

Fixes inline description comment of plat_scmi_clock_rates_array()
and scmi_smt_init_agent_channel().

Acked-by: Jens Wiklander <jens.wiklander@linaro.or

drivers: scmi-msg: correct inline description

Fixes inline description comment of plat_scmi_clock_rates_array()
and scmi_smt_init_agent_channel().

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: decrease register size for gicv2

The mapped size for GIC distributor and cpu registers is currently
defined to the size used for GICv3. GICv2 doesn't need such large sizes,
in fact some platfo

core: decrease register size for gicv2

The mapped size for GIC distributor and cpu registers is currently
defined to the size used for GICv3. GICv2 doesn't need such large sizes,
in fact some platforms has the distributor and cpu registers next to
each other in the physical memory map. This causes an overlap that can
be confusing. Fix this by selecting a smaller size when a GICv2 is used
instead.

It should be noted GICC_DIR is at offset 0x1000 in the cpu interface so
this register will not be accessible, but this should not be a problem
since OP-TEE doesn't use that register.

Reviewed-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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tpm2: Add TPM2 as PCR provider to TCG eventlog parsing framework

TCG eventlog parsing framework parses the eventlog and extends the
PCR's. For this, it needs a provider for PCR's. Register TPM2 as
a

tpm2: Add TPM2 as PCR provider to TCG eventlog parsing framework

TCG eventlog parsing framework parses the eventlog and extends the
PCR's. For this, it needs a provider for PCR's. Register TPM2 as
a provider to this framework.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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tpm2: Add commands to GetCapability, Read/Extend PCR

Add support for TPM2_PCR_{Read/Extend} and TPM2_GetCapability.
TPM uses PCR for integrity collections. Add support to
read and extend PCR's. For

tpm2: Add commands to GetCapability, Read/Extend PCR

Add support for TPM2_PCR_{Read/Extend} and TPM2_GetCapability.
TPM uses PCR for integrity collections. Add support to
read and extend PCR's. For PCR's some generic information like
number of banks, number of PCR's, supported and active algorithms etc.
is required which can be obtained from TPM using TPM2_GetCapability
command. This information is required at lot of places, so save the
basic capability information with tpm2_chip.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stpmic1: export regulators API in a specific header file

Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator
interface.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: stpmic1: export regulators API in a specific header file

Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator
interface.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers/tpm2: Add TPM2 MMIO driver

Add support for platforms that interface with TPM2 via
MMIO using FIFO protocol.

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Cho

drivers/tpm2: Add TPM2 MMIO driver

Add support for platforms that interface with TPM2 via
MMIO using FIFO protocol.

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers/tpm2: Add basic TPM2 support in OP-TEE

TPM2 driver introduced in this commit is based on TPM TCG
specification [1] & [2].

The APIs exposed allows to send commands and receive response
from

drivers/tpm2: Add basic TPM2 support in OP-TEE

TPM2 driver introduced in this commit is based on TPM TCG
specification [1] & [2].

The APIs exposed allows to send commands and receive response
from a TPM2 chip.

[1] TCG PC Client Platform TPM Profile Specification for TPM 2.0
Vesrion 1.0.5 Revision 14
[2] TCG PC Client Device Driver Design Principles for TPM 2.0
Version 1.1 Revision 0.04

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_iwdg: implementation of independent watchdog

Implements independent watchdog (IWDG) driver to help detecting
malfunctions due to software or hardware failures. IWDG instances
are cloc

drivers: stm32_iwdg: implementation of independent watchdog

Implements independent watchdog (IWDG) driver to help detecting
malfunctions due to software or hardware failures. IWDG instances
are clocked by an independent clock and stays active if the main
clock fails.

The driver mandates IWDG instances configuration from an embedded DTB.

For the list of features, refer to the reference manuals at:
https://wiki.st.com/stm32mpu/wiki/STM32MP15_resources

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: add stm32 tamper domain driver

Adds stm32_tamp driver for stm32mp1 TAMP sub-system. The implementation
only covers probing of the driver upon embedded DTB content and enabling
some secure c

drivers: add stm32 tamper domain driver

Adds stm32_tamp driver for stm32mp1 TAMP sub-system. The implementation
only covers probing of the driver upon embedded DTB content and enabling
some secure configuration.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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clk: stm32mp13: Introduce STM32MP13 clocks platform

This driver uses a clk-stm32-core API to manage STM32 gates, dividers
and muxes.
The goal of this first patch is to parse the device tree and init

clk: stm32mp13: Introduce STM32MP13 clocks platform

This driver uses a clk-stm32-core API to manage STM32 gates, dividers
and muxes.
The goal of this first patch is to parse the device tree and initialize
a platform data to configure the clock tree.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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dt-bindings: stm32: add stm32mp13 clock and reset bindings

Add new clocks and reset binding files to manage STM32MP13 RCC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ga

dt-bindings: stm32: add stm32mp13 clock and reset bindings

Add new clocks and reset binding files to manage STM32MP13 RCC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: rtc: add RTC API

This API allows to interact with a RTC registered as the system RTC.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@l

drivers: rtc: add RTC API

This API allows to interact with a RTC registered as the system RTC.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt

drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt_driver provider and
with stm32mp1 platform legacy reset control API function:
stm32_reset_assert(), stm32_reset_deassert() and
stm32_reset_assert_deassert_mcu().

This change also removes source file stm32mp1_rcc.c that has moved
to drivers/rstctrl/stm32_rstctrl.c but stm32_rcc_base() definition
which is moved into to platform main.c.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), c

plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), check that they are not NULL, call either
gic_init() or gic_init_base_addr().

We can move most of this logic into gic_init_base_addr(), while
platform-specific code will supply only base physical addresses for
distributor and CPU interface. This will simplify and align platform
code.

ST32MP1 had more complex logic, as it used io_pa_or_va_secure() to get
MMIO range addresses. However, as main_init_gic() called
assert(cpu_mmu_enabled()), there is no sense in using
io_pa_or_va_secure(), because we already ensured that VA will be
always used. Thus assert() call was moved to gic_init_base_addr(), and
STM32MP1 were aligned with other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: wdt: add SMC handler for arm-smc-wdt Linux driver

Add SMC handler to handle SMC coming from Linux arm-smc-wdt driver.
This function is meant to be called in sm_platform_handler() since
CFG_

drivers: wdt: add SMC handler for arm-smc-wdt Linux driver

Add SMC handler to handle SMC coming from Linux arm-smc-wdt driver.
This function is meant to be called in sm_platform_handler() since
CFG_WDT_SM_HANDLER_ID is going to be defined by the platforms.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: wdt: add watchdog interface

Add necessary code to register a system watchdog. This watchdog will
then used for generic watchdog usage using a new simple watchdog interface.
This interface w

drivers: wdt: add watchdog interface

Add necessary code to register a system watchdog. This watchdog will
then used for generic watchdog usage using a new simple watchdog interface.
This interface will be used by SMC handler which will allow handling SMC
coming from the arm-smc-wdt compatible driver present in Linux.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: pm: add support for setting suspend mode

PSCI allows entering platform suspend with SYSTEM_SUSPEND call which
is meant to enter the system in its deepest power state. sama5d2
platform supp

plat-sam: pm: add support for setting suspend mode

PSCI allows entering platform suspend with SYSTEM_SUSPEND call which
is meant to enter the system in its deepest power state. sama5d2
platform supports multiple suspend power states. Currently, Linux
supports the atmel.pm_modes command line option which allows to select
this suspend state. Since Linux uses PSCI SYSTEM_SUSPEND to enter
suspend mode, we are not able to pass information (such as done for
CPU_SUSPEND). In order to select the mode that will be entered by
SYSTEM_SUSPEND from normal world and thus select the desired suspend state,
SMCs are added to allow selecting and getting this power mode.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: atmel_saic: add SAIC driver

Add a driver to handle interrupt that are targeting the secure
interrupt controller. This driver will be used to handle watchdog and
matrix interrupts.

Acked-by

drivers: atmel_saic: add SAIC driver

Add a driver to handle interrupt that are targeting the secure
interrupt controller. This driver will be used to handle watchdog and
matrix interrupts.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: pm: sam: add suspend support

Add suspend support for sama5d2 platform. This support allows to use
all the available modes of suspend present on the sama5d2 platform:
- STANDBY
- ULP0
- ULP0

drivers: pm: sam: add suspend support

Add suspend support for sama5d2 platform. This support allows to use
all the available modes of suspend present on the sama5d2 platform:
- STANDBY
- ULP0
- ULP0 Fast
- ULP1
- BACKUP

By default, STANDBY mode is used as default suspend mode.
This support is meant to be used by PSCI.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: stm32_uart: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock referen

drivers: stm32_uart: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates STM32 UART driver and
platform stm32mp1 console support.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_i2c: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock referenc

drivers: stm32_i2c: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates I2C driver and PMIC
that is a consumer of an I2C bus.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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