drivers: imx_i2c: add support for MX8MQ

Add support for iMX8MQ.

Signed-off-by: David Griego <david.griego@foundries.io>
Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklande

drivers: imx_i2c: add support for MX8MQ

Add support for iMX8MQ.

Signed-off-by: David Griego <david.griego@foundries.io>
Reviewed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core_mmu: fix implicit behavior of core_mmu_add_mapping()

In core_mmu_add_mapping() requested physical address
rounded up/down to granule size (0x100000), which leads
to establishing of virtual mapp

core_mmu: fix implicit behavior of core_mmu_add_mapping()

In core_mmu_add_mapping() requested physical address
rounded up/down to granule size (0x100000), which leads
to establishing of virtual mappings with overlapped
physical counterparts. If two virtual mappings overlaps
due to such roundings, then following phys_to_virt() can
implicitly return result of virtual address from
unexpected mapping. This patch fix such behavior by
returning virtual address of newly established mapping.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>

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drivers:caam: Update DRVCRYPT_OID_MB_US_RSADSI macro with correct value

This macro forms the HASH OID for MD5 algorithm,

It is defined as:
id-md5 OBJECT IDENTIFIER ::= {
iso(1) member-body(2) us(

drivers:caam: Update DRVCRYPT_OID_MB_US_RSADSI macro with correct value

This macro forms the HASH OID for MD5 algorithm,

It is defined as:
id-md5 OBJECT IDENTIFIER ::= {
iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 5
}

According to OpenSSL,
iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 5
part is encoded as
0x2A,0x86,0x48,0x86,0xF7,0x0D,0x02,0x05

Links for reference:
OpenSSL: https://bit.ly/3hVZ7Is
RFC: https://datatracker.ietf.org/doc/html/rfc8017#section-9.2[Page 46]

But in this case it was being formed as
0x2A,0x86,0x48,0x86,0x48,0x02,0x05 which was wrong.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: scif: update base address in scif_uart_init()

Prior this patch function scif_uart_init() didn't called io_pa_or_va()
to determine correct base address for the device. This worked fine
becau

drivers: scif: update base address in scif_uart_init()

Prior this patch function scif_uart_init() didn't called io_pa_or_va()
to determine correct base address for the device. This worked fine
because in most cases OP-TEE address space is identity mapped. But,
this breaks if are trying to enable ASLR, because SCIF MMIO range is
no more 1:1 mapped.

To fix this we need to use io_pa_or_va() as all other drivers do.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: fix CMAC data input handling

Depending on the memory buffer input configuration, the function
caam_dmaobj_sgtbuf_build() might modify the data size to be processed in
the loop.
This c

drivers: caam: fix CMAC data input handling

Depending on the memory buffer input configuration, the function
caam_dmaobj_sgtbuf_build() might modify the data size to be processed in
the loop.
This case happens sometimes on the imx8mp where the input buffer
physical address in above 32 bits.
This implies reporting the data size re-ajustment when data is saved in
the context buffer.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: remove faulty DMAOJB_TRACE()

Remove DMA object debug trace that would print a structure
variable through a NULL pointer.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed

drivers: caam: remove faulty DMAOJB_TRACE()

Remove DMA object debug trace that would print a structure
variable through a NULL pointer.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: add support for mx8mp platforms

Add support for mx8mp in the CAAM HAL.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
A

drivers: caam: add support for mx8mp platforms

Add support for mx8mp in the CAAM HAL.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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imx: pm: add support for reset2 function

Add support for SYSTEM_RESET2, which asserts WDOG-generated reset signal
WDOG_RESET_B_DEB (internal reset).

For additional details check WDOGx_WCR fields de

imx: pm: add support for reset2 function

Add support for SYSTEM_RESET2, which asserts WDOG-generated reset signal
WDOG_RESET_B_DEB (internal reset).

For additional details check WDOGx_WCR fields description in iMX
Applications Processor Reference Manual.

Acked-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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drivers: gic_it_enable(): remove assert that itr is disabled

Prior to this patch there was an assert in gic_it_enable() that non-SGI
interrupts where disabled before this function would enable that

drivers: gic_it_enable(): remove assert that itr is disabled

Prior to this patch there was an assert in gic_it_enable() that non-SGI
interrupts where disabled before this function would enable that
interrupt. This forces the caller to keep track of the state of the
interrupt in question and may also require additional locking to avoid
races around this assert. Enabling an interrupt twice is unnecessary,
but quite harmless. So remove the assert to simplify things for the
caller where possible.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: implement NXP CAAM Driver - DSA

Add DSA CAAM drivers.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Foris

drivers: caam: implement NXP CAAM Driver - DSA

Add DSA CAAM drivers.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: append RSA to CAAM prime driver

Rename caam_prime.c to caam_prime_rsa.c
Rename struct prime_data {} to struct prime_data_rsa {}
Rename caam_prime_gen() to caam_prime_rsa_gen()

The re

drivers: caam: append RSA to CAAM prime driver

Rename caam_prime.c to caam_prime_rsa.c
Rename struct prime_data {} to struct prime_data_rsa {}
Rename caam_prime_gen() to caam_prime_rsa_gen()

The reason why specifying the RSA algorithm for the current CAAM prime
implementation is to prepare the merge for DSA algorithm that will
feature a different prime generation implementation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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drivers: crypto: implement crypto device driver - DSA

Add a generic cryptographic DSA driver interface connecting
TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric

drivers: crypto: implement crypto device driver - DSA

Add a generic cryptographic DSA driver interface connecting
TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: implement NXP CAAM Driver - DH

Add DH CAAM driver.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carrier

drivers: caam: implement NXP CAAM Driver - DH

Add DH CAAM driver.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: crypto: implement crypto driver - DH

Add a generic cryptographic DH driver interface connecting
TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric.neveux@n

drivers: crypto: implement crypto driver - DH

Add a generic cryptographic DH driver interface connecting
TEE Crypto generic APIs to HW driver interface

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: fix CMAC update operation

Fix an issue in the CMAC do_update() operation that
would happen in the following conditions:
* a data temporay buffer full (16 bytes).
* an input message

drivers: caam: fix CMAC update operation

Fix an issue in the CMAC do_update() operation that
would happen in the following conditions:
* a data temporay buffer full (16 bytes).
* an input message of 16 bytes.

These conditions would set the data size to be processed by the CAAM
equals to zero. This would result on the loss of 16 bytes of the input
message and a wrong CMAC.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: fix input data size for CMAC do_update()

Fix a corner case where the CAAM would try to allocate an input
DMA object with a size of 0 bytes.

Signed-off-by: Cedric Neveux <cedric.neveu

drivers: caam: fix input data size for CMAC do_update()

Fix a corner case where the CAAM would try to allocate an input
DMA object with a size of 0 bytes.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: sp805_wdt: use itr_alloc_add()

This change updates sp805_wdt driver to use itr_alloc_add()
since the driver allocates interrupt handlers at runtime.

Signed-off-by: Ludovic Barre <ludovic.b

drivers: sp805_wdt: use itr_alloc_add()

This change updates sp805_wdt driver to use itr_alloc_add()
since the driver allocates interrupt handlers at runtime.

Signed-off-by: Ludovic Barre <ludovic.barre@foss.st.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt: take account type of interrupt in dt_get_irq()

Interrupt DT binding is defined by at least 2 cells as per DT binding
documentation [1]:
```
-The 1st cell is the interrupt type; 0 for SPI i

core: dt: take account type of interrupt in dt_get_irq()

Interrupt DT binding is defined by at least 2 cells as per DT binding
documentation [1]:
```
-The 1st cell is the interrupt type; 0 for SPI interrupts,
1 for PPI interrupts.
-The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987].
PPI interrupts are in the range [0-15].
```

This patch takes the first cell into account to return absolute value
required for itr_enable() interface.

Update CAAM crypto driver accordingly.

Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml?h=v5.9#n66
Signed-off-by: Ludovic Barre <ludovic.barre@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: dt: split dt_get_irq() between interrupt framework and drivers

To welcome other interrupt drivers (coming from other platform for
example), we need to rework dt_get_irq() which was dedicated t

core: dt: split dt_get_irq() between interrupt framework and drivers

To welcome other interrupt drivers (coming from other platform for
example), we need to rework dt_get_irq() which was dedicated to ARM
platform more specifically GIC driver.
This change moves dt_get_irq() in interrupt framework, this manages the
generic part of interrupt bindings (specified by devicetree.org [1]) and
then call a driver callback to translate specific properties.
This callback is registered by drivers while its init step.

Update CAAM crypto driver accordingly.

Link: [1] https://www.devicetree.org/specifications/
Signed-off-by: Ludovic Barre <ludovic.barre@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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drivers: se050: Fix incorrect handling of se050 cipher operation mode

A boolean encrypt flag was being passed to the cipher init function
that instead expects a TEE_OperationMode enum. Given that th

drivers: se050: Fix incorrect handling of se050 cipher operation mode

A boolean encrypt flag was being passed to the cipher init function
that instead expects a TEE_OperationMode enum. Given that the enum
TEE_MODE_ENCRYPT has as a value of 0, encrypt and decrypt operations
were effectively swapped. This error has no practical effect on current
se050 mainline code because the only AES mode currently supported for
se050 is CTR, which ignores the passed value and always performs an
encrypt. But it needs to be fixed before adding support for ECB or CBC,
for example.

Signed-off-by: Dave Herron <dave.herron@gallagher.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.org>

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drivers: scmi-msg: add scmi_smt_set_shared_buffer()

Dynamically set/release SCMI SMT shared buffer reference. This can be
used when the caller passes the SCMI SMT shared memory reference as part
of

drivers: scmi-msg: add scmi_smt_set_shared_buffer()

Dynamically set/release SCMI SMT shared buffer reference. This can be
used when the caller passes the SCMI SMT shared memory reference as part
of OP-TEE invocation parameters instead of using a statically allocated
buffer.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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drivers: scmi-msg: stub exported API functions

Stub exported API functions from SCMI message drivers to make
the implementation more flexible.

Signed-off-by: Etienne Carriere <etienne.carriere@lina

drivers: scmi-msg: stub exported API functions

Stub exported API functions from SCMI message drivers to make
the implementation more flexible.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: implement NXP CAAM Driver - ECC

Add ECC CAAM driver.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklande

drivers: caam: implement NXP CAAM Driver - ECC

Add ECC CAAM driver.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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driver: bcm_sotp: changed driver_init to service_init

bcm_sotp should be available early in optee boot.
which is achieved by making it as service.

Reviewed-by: Etienne Carriere <etienne.carriere@li

driver: bcm_sotp: changed driver_init to service_init

bcm_sotp should be available early in optee boot.
which is achieved by making it as service.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Vahid Dukandar <vahidd@microsoft.com>

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drivers: caam: add missing SCFGR offset for LS platforms

Add missing CAAM security configuration register offset for LS
platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Sah

drivers: caam: add missing SCFGR offset for LS platforms

Add missing CAAM security configuration register offset for LS
platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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