1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * Copyright (c) 2019, Arm Limited. All rights reserved. 5 */ 6 #ifndef ARM_H 7 #define ARM_H 8 9 #include <util.h> 10 11 /* MIDR definitions */ 12 #define MIDR_PRIMARY_PART_NUM_SHIFT 4 13 #define MIDR_PRIMARY_PART_NUM_WIDTH 12 14 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1) 15 16 #define MIDR_IMPLEMENTER_SHIFT 24 17 #define MIDR_IMPLEMENTER_WIDTH 8 18 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1) 19 #define MIDR_IMPLEMENTER_ARM 0x41 20 21 #define CORTEX_A7_PART_NUM 0xC07 22 #define CORTEX_A8_PART_NUM 0xC08 23 #define CORTEX_A9_PART_NUM 0xC09 24 #define CORTEX_A15_PART_NUM 0xC0F 25 #define CORTEX_A17_PART_NUM 0xC0E 26 #define CORTEX_A57_PART_NUM 0xD07 27 #define CORTEX_A72_PART_NUM 0xD08 28 #define CORTEX_A73_PART_NUM 0xD09 29 #define CORTEX_A75_PART_NUM 0xD0A 30 31 /* MPIDR definitions */ 32 #define MPIDR_AFFINITY_BITS 8 33 #define MPIDR_AFFLVL_MASK 0xff 34 #define MPIDR_AFF0_SHIFT 0 35 #define MPIDR_AFF0_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT) 36 #define MPIDR_AFF1_SHIFT 8 37 #define MPIDR_AFF1_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) 38 #define MPIDR_AFF2_SHIFT 16 39 #define MPIDR_AFF2_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) 40 41 #define MPIDR_MT_SHIFT 24 42 #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT) 43 44 #define MPIDR_CPU_MASK MPIDR_AFF0_MASK 45 #define MPIDR_CLUSTER_SHIFT MPIDR_AFF1_SHIFT 46 #define MPIDR_CLUSTER_MASK MPIDR_AFF1_MASK 47 48 #define MPIDR_AARCH32_AFF_MASK (MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | \ 49 MPIDR_AFF2_MASK) 50 51 /* CLIDR definitions */ 52 #define CLIDR_LOUIS_SHIFT 21 53 #define CLIDR_LOC_SHIFT 24 54 #define CLIDR_FIELD_WIDTH 3 55 56 /* CSSELR definitions */ 57 #define CSSELR_LEVEL_SHIFT 1 58 59 /* CTR definitions */ 60 #define CTR_CWG_SHIFT 24 61 #define CTR_CWG_MASK 0xf 62 #define CTR_ERG_SHIFT 20 63 #define CTR_ERG_MASK 0xf 64 #define CTR_DMINLINE_SHIFT 16 65 #define CTR_DMINLINE_WIDTH 4 66 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 67 #define CTR_L1IP_SHIFT 14 68 #define CTR_L1IP_MASK 0x3 69 #define CTR_IMINLINE_SHIFT 0 70 #define CTR_IMINLINE_MASK 0xf 71 #define CTR_WORD_SIZE 4 72 73 #define ARM32_CPSR_MODE_MASK 0x1f 74 #define ARM32_CPSR_MODE_USR 0x10 75 #define ARM32_CPSR_MODE_FIQ 0x11 76 #define ARM32_CPSR_MODE_IRQ 0x12 77 #define ARM32_CPSR_MODE_SVC 0x13 78 #define ARM32_CPSR_MODE_MON 0x16 79 #define ARM32_CPSR_MODE_ABT 0x17 80 #define ARM32_CPSR_MODE_UND 0x1b 81 #define ARM32_CPSR_MODE_SYS 0x1f 82 83 #define ARM32_CPSR_T (1 << 5) 84 #define ARM32_CPSR_F_SHIFT 6 85 #define ARM32_CPSR_F (1 << 6) 86 #define ARM32_CPSR_I (1 << 7) 87 #define ARM32_CPSR_A (1 << 8) 88 #define ARM32_CPSR_E (1 << 9) 89 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 90 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 91 #define ARM32_CPSR_IT_MASK1 0x06000000 92 #define ARM32_CPSR_IT_MASK2 0x0000fc00 93 94 /* ARM Generic timer definitions */ 95 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 96 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 97 98 #ifdef ARM32 99 #include <arm32.h> 100 #endif 101 102 #ifdef ARM64 103 #include <arm64.h> 104 #endif 105 106 #ifndef __ASSEMBLER__ 107 static inline __noprof uint64_t barrier_read_counter_timer(void) 108 { 109 isb(); 110 #ifdef CFG_CORE_SEL2_SPMC 111 return read_cntvct(); 112 #else 113 return read_cntpct(); 114 #endif 115 } 116 #endif 117 118 #endif /*ARM_H*/ 119