drivers: imx_wdog: fix compilation warning on watchdog driver

$ make PLATFORM=imx-mx7ulpevk CFG_DT=n
core/drivers/imx_wdog.c:42:13: warning: ext_reset_output defined but not used [-Wunused-variable]

drivers: imx_wdog: fix compilation warning on watchdog driver

$ make PLATFORM=imx-mx7ulpevk CFG_DT=n
core/drivers/imx_wdog.c:42:13: warning: ext_reset_output defined but not used [-Wunused-variable]
42 | static bool ext_reset_output;
| ^~~~~~~~~~~~~~~~

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: fix aligned buffer allocation for DMA

For aligned memory buffer and DMA CAAM access, the allocated buffer size
must be rounded up to a certain value depending of the DMA behaviour on

drivers: caam: fix aligned buffer allocation for DMA

For aligned memory buffer and DMA CAAM access, the allocated buffer size
must be rounded up to a certain value depending of the DMA behaviour on
the platform.
For the imx8qm/qxp, the allocated aligned buffer size must be rounded up
to 4 bytes.

Signed-off-by: Remi Koman <remi.koman@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: clk: move stm32mp1 clock driver to clock drivers directory

Moves stm32mp15 clock driver to core/drivers/clk and adds configuration
switch CFG_STM32MP15_CLK to embed or not the driver. Platf

drivers: clk: move stm32mp1 clock driver to clock drivers directory

Moves stm32mp15 clock driver to core/drivers/clk and adds configuration
switch CFG_STM32MP15_CLK to embed or not the driver. Platform stm32mp1
mandates CFG_STM32MP15_CLK=y.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: add reset controller framework

Adds a common reset controller framework rstctrl for interfacing
reset controllers exposed by a platform.

Reset controller consumers can act on relate reset

drivers: add reset controller framework

Adds a common reset controller framework rstctrl for interfacing
reset controllers exposed by a platform.

Reset controller consumers can act on relate reset level with
rstctrl_assert(), rstctrl_deassert() and friends.

Reset controller consumers can claim exclusive access to the reset
level woth rstctrl_get_exclusive(), rstctrl_put_exclusive().

Reset controller provider drivers call rstctrl_register_provider()
to allow other drivers to get a reset control reference from
a devicetree reference. Reset controller driver are identified with
type DT_DRIVER_RSTCTRL.

A reset controller provider exposes struct rstctrl instances made of
an opaque private reference (a private data pointer or an unsigned
integer identifier), an reset controller operators reference and
the exclusive claim state.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: define DT drivers using scattered arrays

Replace the specific mechanism used to define and enumerate DT drivers
with scattered arrays. Doing so simplifies the TEE linker file a bit.

Signed-of

core: define DT drivers using scattered arrays

Replace the specific mechanism used to define and enumerate DT drivers
with scattered arrays. Doing so simplifies the TEE linker file a bit.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto: drivers: se050: ecc shared secret

Allow clients to inject their own keypairs to derive the secret - the
previous implementation only allowed for secure element NVM based
keypairs to be used.

crypto: drivers: se050: ecc shared secret

Allow clients to inject their own keypairs to derive the secret - the
previous implementation only allowed for secure element NVM based
keypairs to be used.

By default, the secure element does not store all the possible EC
curves in its internal memory; however attempting to inject a keypair
when the curve is not in the secure element would cause the injection
to fail.

This commit addresses that situation by generating those curves in the
SE whenever they are not available.

Tested with TEE_ALG_ECDH_P192, TEE_ALG_ECDH_P224, TEE_ALG_ECDH_P256
and TEE_ALG_ECDH_P384 and TEE_ALG_ECDH_P521 (xtest 4009 passing)

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: rsa: handle not implemented sign/verify operations

Route the unimplemented RSA sign/verify optional cases to their
software implementations.

Signed-off-by: Jorge Ramirez-Ortiz <jor

drivers: crypto: rsa: handle not implemented sign/verify operations

Route the unimplemented RSA sign/verify optional cases to their
software implementations.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM registers for imx8q platforms

Add CAAM register definitions for the following platforms:
* imx8qm
* imx8qxp

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by:

drivers: caam: add CAAM registers for imx8q platforms

Add CAAM register definitions for the following platforms:
* imx8qm
* imx8qxp

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: hal: add the support for imx8q

Add the CAAM HAL for the following platforms:
- imx8qm
- imx8qxp

These platforms feature a separate security controller that handles
the following re

drivers: caam: hal: add the support for imx8q

Add the CAAM HAL for the following platforms:
- imx8qm
- imx8qxp

These platforms feature a separate security controller that handles
the following resources/peripherals:
- RNG
- Peripheral owernership
- Clocks

To allocate and initialize the CAAM, the driver relies on the
MU driver and a secure controller API to communicate with the
security controller.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: hal: make common initialization functions overideable

Define the following functions as weak:
* caam_hal_rng_instantiated()
* caam_hal_cfg_setup_nsjobring()

Add CAAM CAAM_NOT_INIT

drivers: caam: hal: make common initialization functions overideable

Define the following functions as weak:
* caam_hal_rng_instantiated()
* caam_hal_cfg_setup_nsjobring()

Add CAAM CAAM_NOT_INIT code for CAAM RNG initialization status.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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crypto: drivers: se050: fix rsa encrypt/decrypt

- Fix input/output buffers (they were swapped).
- Fix algorithm selection for RSAES

Test:
openssl rsautl -encrypt -inkey rsa-pubkey.pub \

crypto: drivers: se050: fix rsa encrypt/decrypt

- Fix input/output buffers (they were swapped).
- Fix algorithm selection for RSAES

Test:
openssl rsautl -encrypt -inkey rsa-pubkey.pub \
-in data -pubin -out data.crypt

pkcs11-tool --module /usr/lib/libckteec.so.0.1 \
--pin 87654321 --decrypt --id 01 \
--token-label fio --mechanism RSA-PKCS \
--input-file data.crypt > data.decrypted

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@forissier.org>

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crypto: drivers: se050: OEFID runtime detection

The CFG_CORE_SE05X_OEFID definition is not required as the SE05X OEFID
can be read during early init - before the SCP03 session has been
established.

crypto: drivers: se050: OEFID runtime detection

The CFG_CORE_SE05X_OEFID definition is not required as the SE05X OEFID
can be read during early init - before the SCP03 session has been
established.

The user we can continue to define its value so that the OP-TEE driver
only works when such OEFID is available.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@forissier.org>

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crypto: drivers: se050: ecc sign

The crypto API validates the size of the buffer that will hold the
resulting signature. This means that the SE05X driver can not use the
variable length buffer mecha

crypto: drivers: se050: ecc sign

The crypto API validates the size of the buffer that will hold the
resulting signature. This means that the SE05X driver can not use the
variable length buffer mechanism to request extra bytes to handle the
DER format.

To address this situation, this patch allocates a temporary buffer to
get the signature from the Plug-and-Trust subsystem; then, upon doing
the DER to binary conversion, copies the resulting data to the output
buffer.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: atmel-shdwc: add atmel shdwc driver

Add atmel shdwc driver for sama5d2. This driver uses assembly code
which expects to run from a single cache line. For the time being,
building this code

drivers: atmel-shdwc: add atmel shdwc driver

Add atmel shdwc driver for sama5d2. This driver uses assembly code
which expects to run from a single cache line. For the time being,
building this code is restricted to single core system since it rely
on the fact that no other cores can invalidate the TLB or the
I-cache. This driver will be used by PSCI to shutdown the SoC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: clk: sam: expose at91_pmc_get_base

The shutdown controller needs to access the PMC to switch the clock
using assembly code. Expose pmc base using at91_pmc_get_base.

Acked-by: Etienne Carri

drivers: clk: sam: expose at91_pmc_get_base

The shutdown controller needs to access the PMC to switch the clock
using assembly code. Expose pmc base using at91_pmc_get_base.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: clk: use while (true)

Changes clk_dt.c to use while (true) instead of while (1) for consistency
in optee_os implementation.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-

drivers: clk: use while (true)

Changes clk_dt.c to use while (true) instead of while (1) for consistency
in optee_os implementation.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: change clk_dt_get_by_*() prototype

Changes clk_dt_get_by_idx() and clk_dt_get_by_name() to return a
the TEE_Result code and use an output argument to pass back
clock reference rather t

drivers: clk: change clk_dt_get_by_*() prototype

Changes clk_dt_get_by_idx() and clk_dt_get_by_name() to return a
the TEE_Result code and use an output argument to pass back
clock reference rather than the opposite. This change makes
clk_dt_get_by_*() function more consistent with the other
OP-TEE core API functions.

Also renames clk_dt_get_by_idx() to clk_dt_get_by_index().

Updates sama5d2_clk.c and atmel_trng.c accordingly.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: caam: acipher: initialize driver with the JR base address

Instead of systematically using the job ring 0 registers to initialize
the CAAM acipher drivers, use the job ring allocated to OPTE

drivers: caam: acipher: initialize driver with the JR base address

Instead of systematically using the job ring 0 registers to initialize
the CAAM acipher drivers, use the job ring allocated to OPTEE OS.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: caam: hash: initialize driver with the JR base address

Instead of systematically using the job ring 0 registers to initialize
the CAAM hash driver, use the job ring allocated to OPTEE OS.

drivers: caam: hash: initialize driver with the JR base address

Instead of systematically using the job ring 0 registers to initialize
the CAAM hash driver, use the job ring allocated to OPTEE OS.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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driver: atmel_trng: remove wrong assertion

Remove mistakenly added assert which will always trigger in debug
mode.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <cl

driver: atmel_trng: remove wrong assertion

Remove mistakenly added assert which will always trigger in debug
mode.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: imx: add SC driver for i.MX8QM/QXP

Add the secure controller driver that implements:
- SCFW API
- SCU IPC functions
- SCU secure IPC initialization
The SCU driver relies on the MU driver

drivers: imx: add SC driver for i.MX8QM/QXP

Add the secure controller driver that implements:
- SCFW API
- SCU IPC functions
- SCU secure IPC initialization
The SCU driver relies on the MU driver to communicate with the security
controller.

Signed-off-by: Remi Koman <remi.koman@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: imx_wdog: fix defined but not used with CFG_DT=n

Fix a defined but not used error when building with CFG_DT by moving
dt_wdog_match_table under the same ifdef block used by the device-tree

drivers: imx_wdog: fix defined but not used with CFG_DT=n

Fix a defined but not used error when building with CFG_DT by moving
dt_wdog_match_table under the same ifdef block used by the device-tree
block.

Acked-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>

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drivers: atmel-rstc: add support for reset controller

This reset controller will be used by PSCI to reset the SoC.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <j

drivers: atmel-rstc: add support for reset controller

This reset controller will be used by PSCI to reset the SoC.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: stm32_cryp: prevent error trace when disabled

Changes stm32_crypt initialization function to not report an error
when the device is not defined or disabled in the embedded DT.

Prevents err

drivers: stm32_cryp: prevent error trace when disabled

Changes stm32_crypt initialization function to not report an error
when the device is not defined or disabled in the embedded DT.

Prevents error trace message seen at boot time:
E/TC:0 0 call_initcalls:43 Initcall __text_start + 0x0002b958 failed

Fixes: 5c3bcc386415 ("dts: stm32mp1: disable CRYP1 device")
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: add Atmel TRNG driver

This driver uses the device tree to probe the TRNG and then allows
random data to be queried using both hw_get_random_byte() and
crypto_rng_read().

Acked-by: Etienne

drivers: add Atmel TRNG driver

This driver uses the device tree to probe the TRNG and then allows
random data to be queried using both hw_get_random_byte() and
crypto_rng_read().

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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