drivers: crypto: stm32_cryp: use rstctrl resources

Changes stm32_cryp driver to use rstctrl resources. Driver panics
upon rstctrl_dt_get_by_index() failure, even in case of driver probe
deferral err

drivers: crypto: stm32_cryp: use rstctrl resources

Changes stm32_cryp driver to use rstctrl resources. Driver panics
upon rstctrl_dt_get_by_index() failure, even in case of driver probe
deferral error as stm32_cryp is not yet defined as a DT_DRIVER. Such
port is out of the scope this change.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt

drivers: stm32_rstctrl reset controller for stm32mp1 platforms

Implement stm32 platforms reset controller device, embedded upon
CFG_STM32_RSTCTRL=y.

The drivers exposes its reset controls to the dt_driver provider and
with stm32mp1 platform legacy reset control API function:
stm32_reset_assert(), stm32_reset_deassert() and
stm32_reset_assert_deassert_mcu().

This change also removes source file stm32mp1_rcc.c that has moved
to drivers/rstctrl/stm32_rstctrl.c but stm32_rcc_base() definition
which is moved into to platform main.c.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: crypto: add parameter checks for RSA signature

Add size check in the crypto driver for RSA sign and verify functions.
For both functions, the encoded message length has some size
constraint

drivers: crypto: add parameter checks for RSA signature

Add size check in the crypto driver for RSA sign and verify functions.
For both functions, the encoded message length has some size
constraints [1].

[1]: Public-Key Cryptography Standards (PKCS) #1: RSA Cryptography
https://datatracker.ietf.org/doc/html/rfc3447#section-9.1.1

Fixes: f5a70e3ef ("drivers: crypto: generic resources for crypto device driver - RSA")
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: gic: replace spaces with tabs

No functional changes.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etie

drivers: gic: replace spaces with tabs

No functional changes.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), c

plat: arm: refactor GIC initialization

All platforms (except STM32MP1) follow the same pattern during GIC
initialization: get virtual addresses for distributor (and optionally,
for CPU interface), check that they are not NULL, call either
gic_init() or gic_init_base_addr().

We can move most of this logic into gic_init_base_addr(), while
platform-specific code will supply only base physical addresses for
distributor and CPU interface. This will simplify and align platform
code.

ST32MP1 had more complex logic, as it used io_pa_or_va_secure() to get
MMIO range addresses. However, as main_init_gic() called
assert(cpu_mmu_enabled()), there is no sense in using
io_pa_or_va_secure(), because we already ensured that VA will be
always used. Thus assert() call was moved to gic_init_base_addr(), and
STM32MP1 were aligned with other platforms.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_gpio: Fix register access before enabling clocks

The valid_gpio_config() function accesses the GPIO register
before the clock is enabled, which leads to the assert always
failing when

drivers: stm32_gpio: Fix register access before enabling clocks

The valid_gpio_config() function accesses the GPIO register
before the clock is enabled, which leads to the assert always
failing when using stm32_gpio_set_output_level().

Signed-off-by: Loïc Bauer <loic.bauer@socomec.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: crypto: se050: panic on initialization error

Failure to initialize the SE05x device is a critical operation as it will
effectively disable ciphers configured at build time.

This also match

drivers: crypto: se050: panic on initialization error

Failure to initialize the SE05x device is a critical operation as it will
effectively disable ciphers configured at build time.

This also matches the behaviour implemented by the other crypto drivers.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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crypto/aspeed: ast2600: Add HACE HW hash support

Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.

This patch adds

crypto/aspeed: ast2600: Add HACE HW hash support

Aspeed AST2600 Hash and Crypto Engine (HACE) is designated to
accelerate the throughput of hash and symmetric encryption/decryption.

This patch adds the driver support for AST2600 HACE to provide
HW-assisted hash for the SHA family. The initial driver structure
for Aspeed crypto engines is also constructed.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: atmel_wdt: add atmel watchdog timer driver

Add a driver to handle the atmel watchdog timer that is present on the
sama5d2. This driver allows to use an interrupt handler that for the
moment

drivers: atmel_wdt: add atmel watchdog timer driver

Add a driver to handle the atmel watchdog timer that is present on the
sama5d2. This driver allows to use an interrupt handler that for the
moment does nothing but display the watchdog error.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: wdt: add SMC handler for arm-smc-wdt Linux driver

Add SMC handler to handle SMC coming from Linux arm-smc-wdt driver.
This function is meant to be called in sm_platform_handler() since
CFG_

drivers: wdt: add SMC handler for arm-smc-wdt Linux driver

Add SMC handler to handle SMC coming from Linux arm-smc-wdt driver.
This function is meant to be called in sm_platform_handler() since
CFG_WDT_SM_HANDLER_ID is going to be defined by the platforms.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: wdt: add watchdog interface

Add necessary code to register a system watchdog. This watchdog will
then used for generic watchdog usage using a new simple watchdog interface.
This interface w

drivers: wdt: add watchdog interface

Add necessary code to register a system watchdog. This watchdog will
then used for generic watchdog usage using a new simple watchdog interface.
This interface will be used by SMC handler which will allow handling SMC
coming from the arm-smc-wdt compatible driver present in Linux.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: pm: add support for setting suspend mode

PSCI allows entering platform suspend with SYSTEM_SUSPEND call which
is meant to enter the system in its deepest power state. sama5d2
platform supp

plat-sam: pm: add support for setting suspend mode

PSCI allows entering platform suspend with SYSTEM_SUSPEND call which
is meant to enter the system in its deepest power state. sama5d2
platform supports multiple suspend power states. Currently, Linux
supports the atmel.pm_modes command line option which allows to select
this suspend state. Since Linux uses PSCI SYSTEM_SUSPEND to enter
suspend mode, we are not able to pass information (such as done for
CPU_SUSPEND). In order to select the mode that will be entered by
SYSTEM_SUSPEND from normal world and thus select the desired suspend state,
SMCs are added to allow selecting and getting this power mode.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: caam: instantiate RNG state handle with prediction resistance

Instantiate RNG state handles with Prediction Resistance (PR) support.
This way SW further downstream (e.g. Rich OS, boot loade

drivers: caam: instantiate RNG state handle with prediction resistance

Instantiate RNG state handles with Prediction Resistance (PR) support.
This way SW further downstream (e.g. Rich OS, boot loader etc.) is able
to use the "PR" bit in RNG generation descriptors (forcing TRNG
re-seeding before PRNG / DRBG outputs random data).

Note: current patch does not deal with RNG state handles that have
already been initialized, but without PR support (this could happen if
U-boot would run before OP-TEE etc.). In this case, RNG state handle
would have to be deinstantiated first, and then reinstantiated with
PR support.

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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crypto: drivers: se050: remove implicit dependency

The SE05X device is platform independent and therefore does not need
the iMX I2C driver but the actual driver for the particular platform
is connec

crypto: drivers: se050: remove implicit dependency

The SE05X device is platform independent and therefore does not need
the iMX I2C driver but the actual driver for the particular platform
is connected into.

Implementing these changes required a fix in the Plug-and-Trust tree
(the addition of a missing dependency), therefore we will also bump
the Plug-and-Trust version used in the Azure pipeline.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@forissier.org>

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drivers: atmel_saic: add SAIC driver

Add a driver to handle interrupt that are targeting the secure
interrupt controller. This driver will be used to handle watchdog and
matrix interrupts.

Acked-by

drivers: atmel_saic: add SAIC driver

Add a driver to handle interrupt that are targeting the secure
interrupt controller. This driver will be used to handle watchdog and
matrix interrupts.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: atmel_shdwc: add call to suspend init

Since there is no "suspend" controller per se and that the general
controller used for suspend is the shutdown controller, call suspend
init from shdwc

drivers: atmel_shdwc: add call to suspend init

Since there is no "suspend" controller per se and that the general
controller used for suspend is the shutdown controller, call suspend
init from shdwc driver.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: pm: sam: add suspend support

Add suspend support for sama5d2 platform. This support allows to use
all the available modes of suspend present on the sama5d2 platform:
- STANDBY
- ULP0
- ULP0

drivers: pm: sam: add suspend support

Add suspend support for sama5d2 platform. This support allows to use
all the available modes of suspend present on the sama5d2 platform:
- STANDBY
- ULP0
- ULP0 Fast
- ULP1
- BACKUP

By default, STANDBY mode is used as default suspend mode.
This support is meant to be used by PSCI.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: clk: sam: add suspend support

PMC register contents needs to be restored after resuming. Add support
for this using PM callbacks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
A

drivers: clk: sam: add suspend support

PMC register contents needs to be restored after resuming. Add support
for this using PM callbacks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: stm32_rng: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock referenc

drivers: stm32_rng: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates STM32 RNG driver.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_gpio: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock referen

drivers: stm32_gpio: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates STM32 GPIO driver.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_uart: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock referen

drivers: stm32_uart: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates STM32 UART driver and
platform stm32mp1 console support.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_i2c: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock referenc

drivers: stm32_i2c: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates I2C driver and PMIC
that is a consumer of an I2C bus.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_i2c: stm32_i2c_get_setup_from_fdt() returns TEE_Result

Change stm32_i2c interface function stm32_i2c_get_setup_from_fdt()
to return a TEE_Result code rather than a FDT error code.

Re

drivers: stm32_i2c: stm32_i2c_get_setup_from_fdt() returns TEE_Result

Change stm32_i2c interface function stm32_i2c_get_setup_from_fdt()
to return a TEE_Result code rather than a FDT error code.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: stm32mp15: convert clock reference to clock ID/GPIO bank

Add stm32mp_clock_id_to_clk() to allow some platform specific functions
to act on clock while based only on the clock DT bindin

drivers: clk: stm32mp15: convert clock reference to clock ID/GPIO bank

Add stm32mp_clock_id_to_clk() to allow some platform specific functions
to act on clock while based only on the clock DT binding ID used in
stm32mp1 old clock API functions.

Add stm32_get_gpio_bank_clk() to return the clock reference related to
a GPIO bank.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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crypto: drivers: se050: rsa: sign_ssa error handling

SE NVM keys shall only be deleted using either the pkcs#11 interface
(if the key was created by pkcs#11) or the free_keypair crypto API
interface

crypto: drivers: se050: rsa: sign_ssa error handling

SE NVM keys shall only be deleted using either the pkcs#11 interface
(if the key was created by pkcs#11) or the free_keypair crypto API
interface and never as a result of some error handling operation.

Notice that calling free_keypair will invalidate any copy made of that
keypair since the keypair for a SE only holds a handle to the key
stored in the SE NVM.

Fixes: a3ca687d03b4 ("drivers: implement se050 driver")
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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