drivers: clk: sam: export audiopll_fracck and usbck

This allows to modify the clocks rate and parents from the device-tree
using assigned-clock-parents/rate properties rather than hardcoding the
clo

drivers: clk: sam: export audiopll_fracck and usbck

This allows to modify the clocks rate and parents from the device-tree
using assigned-clock-parents/rate properties rather than hardcoding the
clocks rate.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: clk: sam: add a macro for count of main clocks

Add a macro instead of using clock index name to define the count of main
clocks. This will ease the changes when exposing new clocks.

Signed

drivers: clk: sam: add a macro for count of main clocks

Add a macro instead of using clock index name to define the count of main
clocks. This will ease the changes when exposing new clocks.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: drivers: crypto: caam: Check PKCS_V1_5 decryption buffer size

Check if original buffer is large enough for a result of
RSA PKCS_V1_5 decryption operation.
With this change PKCS11 variable leng

core: drivers: crypto: caam: Check PKCS_V1_5 decryption buffer size

Check if original buffer is large enough for a result of
RSA PKCS_V1_5 decryption operation.
With this change PKCS11 variable length buffers are supported
for all RSA operations:
- Crypto API checks it for PKCS_V1_5 and OAEP encryptions.
- OAEP decryption already supports it.

This fixes: https://github.com/OP-TEE/optee_os/issues/5841

Acked-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Anton Antonov <Anton.Antonov@arm.com>

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drivers: stm32_*: remove code for when DT is not supported

This change removes implementation managing cases when CFG_EMBED_DTB or
CFG_DT are disabled. This change aims to simplify source files and

drivers: stm32_*: remove code for when DT is not supported

This change removes implementation managing cases when CFG_EMBED_DTB or
CFG_DT are disabled. This change aims to simplify source files and is
related to commit [1] from which stm32mp1 platform requires DTB for the
drivers configuration.

Link: [1] 474ad1856b56 ("plat-stm32mp1: conf: mandate the use of device tree on STM32MP1x platforms")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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versal: enable the crypto driver

The crypto driver API provides an extra indirection level to enable
different ciphers.

Since Versal ACAP supports acipher and authenc, enable them.

Falling-back to

versal: enable the crypto driver

The crypto driver API provides an extra indirection level to enable
different ciphers.

Since Versal ACAP supports acipher and authenc, enable them.

Falling-back to software operations (RSA sign/verify) triggers a
fault detection; we will disable this config while a solution is
found.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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crypto: versal: rsa: only support sign/verify operations

RSA encryption/decryption is not supported (the PLM does not
return the size of the encrypted/decrypted buffers).

Signed-off-by: Jorge Ramir

crypto: versal: rsa: only support sign/verify operations

RSA encryption/decryption is not supported (the PLM does not
return the size of the encrypted/decrypted buffers).

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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crypto: versal: ecc: sign/verify fix

Both the message (hash) and the generated signatures must be swapped.

The following custom tests were executed for P384 (prime384v1) and
P521 (nistp521) curves.

crypto: versal: ecc: sign/verify fix

Both the message (hash) and the generated signatures must be swapped.

The following custom tests were executed for P384 (prime384v1) and
P521 (nistp521) curves.

Signing and verifying using pkcs#11 alone (ie like done in xtest) was
not sufficient to capture this bug.

PTOOL='pkcs11-tool --module /usr/lib/libckteec.so.0.1.0'
SO_PIN=55555555
PIN=44444444
FILE=hello

printf "OP-TEE: create key pair"
$PTOOL --id 01 --label ldts --token-label fio --pin $PIN \
--keypairgen \
--key-type EC:prime384v1

printf "OP-TEE: read the public key"
$PTOOL -l --pin $PIN --id 01 \
--read-object --type pubkey --output-file pubkey.spki

printf "Openssl: export key to PEM"
openssl ec -inform DER -outform PEM -in pubkey.spki -pubin > pubkey.pub

printf "Create file to sign"
echo "hello world" > $FILE

printf "OpenSSL: create the file sha384"
openssl dgst -binary -sha384 $FILE > $FILE.hash

printf "OP-TEE: generate signature "
$PTOOL --pin $PIN --id 01 --label ldts --token-label fio \
--sign
--input-file $FILE.hash
--output-file $FILE.sig
--mechanism ECDSA
-f openssl

printf "OpenSSL: verify signature"
openssl dgst -sha384 -verify pubkey.pub -signature "$FILE".sig "$FILE"

printf "OP-TEE: verify signature"
$PTOOL --pin $PIN --id 01 --label ldts --token-label fio \
--verify \
--input-file $FILE.hash \
--signature-format openssl \
--signature-file $FILE.sig \
--mechanism ECDSA

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: drivers: nxp: always disable povdd after trying to fuse the SFP

- The LX series manual specifies that the POVDD pin should always be
reset to GND before powering off or resetting the SoC.
-

core: drivers: nxp: always disable povdd after trying to fuse the SFP

- The LX series manual specifies that the POVDD pin should always be
reset to GND before powering off or resetting the SoC.
- The SFP driver will leave the POVDD pin raised if it encounters an
error while fusing.
- Change SFP driver to always unset POVDD after any fuse attempt.

Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: drivers: nxp: bit shift the ITS and SB bits when reading the SFP

- The Intent to Secure (ITS) and Secure Boot (SB) flags are written to a
given pointer in ls_sfp_get_its() and ls_sfp_get_sb(

core: drivers: nxp: bit shift the ITS and SB bits when reading the SFP

- The Intent to Secure (ITS) and Secure Boot (SB) flags are written to a
given pointer in ls_sfp_get_its() and ls_sfp_get_sb() respectively.
- The written values are equivalent to the entire masked OSPR0 and OSPR1
registers.
- The two functions should instead update a pointer with a boolean
integer containing the bit shifted value of the desired flag.

Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: drivers: nxp: update LX series SFP fuse timeout

- The LX series manual specifies that fusing the SFP can take up to
100ms to complete.
- The fuse timeout in the LS SFP driver should be chang

core: drivers: nxp: update LX series SFP fuse timeout

- The LX series manual specifies that fusing the SFP can take up to
100ms to complete.
- The fuse timeout in the LS SFP driver should be changed to 150ms
so that the possible 100ms timeout has a buffer to interpret errors.

Signed-off-by: Andrew Mustea <andrew.mustea@microsoft.com>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: add driver for hafnium interrupt controller

Adds a driver for the paravirtualized interrupt controller provided by
Hafnium at S-EL2. The driver is enabled with CFG_CORE_HAFNIUM_INTC=y.

The in

core: add driver for hafnium interrupt controller

Adds a driver for the paravirtualized interrupt controller provided by
Hafnium at S-EL2. The driver is enabled with CFG_CORE_HAFNIUM_INTC=y.

The interrupt controller is limited compared to the GIC and only works
with interrupt ids which are already added in the SP manifest or as
predefined reserved interrupt ids.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_rng: make stm32_rng_read() static

Reading a random number should be done via the generic API.

Makes stm32_rng_read() static as it is unused in other files and remove
stm32_rng.h, whi

drivers: stm32_rng: make stm32_rng_read() static

Reading a random number should be done via the generic API.

Makes stm32_rng_read() static as it is unused in other files and remove
stm32_rng.h, which is now empty.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: override plat_rng_init() if hardware RNG

Avoids useless operations by overriding plat_rng_init() and do nothing.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

drivers: stm32_rng: override plat_rng_init() if hardware RNG

Avoids useless operations by overriding plat_rng_init() and do nothing.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: implement late seed error detection

As per STM32MP1x specification, rare seed error conditions must be
considered when random value read from DR register is zero.

Signed-off-by:

drivers: stm32_rng: implement late seed error detection

As per STM32MP1x specification, rare seed error conditions must be
considered when random value read from DR register is zero.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: pm callbacks

Implements power management (suspend/resume) functions in stm32_rng
driver.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Ca

drivers: stm32_rng: pm callbacks

Implements power management (suspend/resume) functions in stm32_rng
driver.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: support clock error detection

Adds clock error detection configuration when the clock-error-detect
property is set in the RNG node in the device tree.

Signed-off-by: Gatien Chev

drivers: stm32_rng: support clock error detection

Adds clock error detection configuration when the clock-error-detect
property is set in the RNG node in the device tree.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: support conditional reset

Implements a RNG variant error concealment named conditional reset
that requires a software sequence before RNG being able to deliver
again random bytes

drivers: stm32_rng: support conditional reset

Implements a RNG variant error concealment named conditional reset
that requires a software sequence before RNG being able to deliver
again random bytes. It is supported by STM32MP13

RNG peripherals that are supporting conditional reset can dynamically
customize their configuration. Adds support for RNG clock frequency
restraint and NIST configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: call conceal_seed_error() on error cases

Changes conceal_seed_error() implementation to be called only upon
error conditions. This change will ease next integration of
STM32MP13

drivers: stm32_rng: call conceal_seed_error() on error cases

Changes conceal_seed_error() implementation to be called only upon
error conditions. This change will ease next integration of
STM32MP13 variant error concealment implementation.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: cleanup and change sample read timeout to 10ms

10ms timeout is sufficient when reading samples from RNG subsystem
when log level is below TRACE_FLOW log level. This changes renam

drivers: stm32_rng: cleanup and change sample read timeout to 10ms

10ms timeout is sufficient when reading samples from RNG subsystem
when log level is below TRACE_FLOW log level. This changes renames
the timeout value macro to RNG_READY_TIMEOUT_US.

This change also renames the reset timeout value for clarity,
from RNG_TIMEOUT_US_1MS to RNG_RESET_TIMEOUT_US.

Moves RNG_FIFO_BYTE_DEPTH macro definition to source file beginning.
Uses U() macro to define IOMEM registers offsets.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: keep rng enable from initialization

Changes stm32_rng driver implementation to keep RNG running and
only gate the access bus clock when accessing RNG interface.

Removes refcount

drivers: stm32_rng: keep rng enable from initialization

Changes stm32_rng driver implementation to keep RNG running and
only gate the access bus clock when accessing RNG interface.

Removes refcount field from stm32_rng_instance structure as it is now
unused.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: register to dt_driver

Changes stm32_rng driver to be probed from DT_DRIVER framework.
This change modifies slightly how the driver is initialized.
Early late initcall function st

drivers: stm32_rng: register to dt_driver

Changes stm32_rng driver to be probed from DT_DRIVER framework.
This change modifies slightly how the driver is initialized.
Early late initcall function stm32_rng_init() is replaced with
a FDT helper function stm32_rng_parse_fdt() and a DT_DRIVER probe
function stm32_rng_probe().

Changes stm32_rng driver initialization sequence to reset, if configured,
the RNG hardware subsystem at driver initialization.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: crypto_api: remove unused includes

Remove unused includes from the crypto API.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

core: crypto_api: remove unused includes

Remove unused includes from the crypto API.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: remove unused includes

Remove unused includes from the CAAM driver.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acke

drivers: caam: remove unused includes

Remove unused includes from the CAAM driver.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto_api: fix malloc() allocation check

Coverity reports a CERT-C ERR33-C coding violation on EM.data pointer
for not being checked right after malloc() call.
This is a false positive error

core: crypto_api: fix malloc() allocation check

Coverity reports a CERT-C ERR33-C coding violation on EM.data pointer
for not being checked right after malloc() call.
This is a false positive error since EM.data value is checked along
EM_gen.data value later.
Check EM.data and EM_gen.data values separately to make Coverity happy.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: se050: increase DER signature buffer

In order to support P-521 (132 byte {r,s} pairs), the buffer storing
the DER signature must be large enough.

Signed-off-by: Jorge Ramirez-Ortiz

drivers: crypto: se050: increase DER signature buffer

In order to support P-521 (132 byte {r,s} pairs), the buffer storing
the DER signature must be large enough.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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