drivers: pm: imx: relocate power management code

Relocate power management functions from plat-imx/pm to
core/drivers/pm/imx

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wikl

drivers: pm: imx: relocate power management code

Relocate power management functions from plat-imx/pm to
core/drivers/pm/imx

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: move PSCI SNVS operation to the driver

Create imx_snvs_shutdown() to use during psci_system_off() call.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jen

core: imx: move PSCI SNVS operation to the driver

Create imx_snvs_shutdown() to use during psci_system_off() call.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto: stm32: fix SAES reset at probe time

Uses SAES internal reset sequence only when external reset controller
is not available. This change fixes a non-systematic SAES error
seen when SAES inter

crypto: stm32: fix SAES reset at probe time

Uses SAES internal reset sequence only when external reset controller
is not available. This change fixes a non-systematic SAES error
seen when SAES internal reset is triggered right after external reset
sequence. Whereas a fix could be to add a delay between external reset
and internal reset sequences, this change simplifies the sequence as
internal reset sequence is not needed when SAES instance is reset using
its external reset controller.

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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driver: gic: support sgi raise for gicv3

Use write_icc_sgi1r() and write_icc_asgi1r() to raise SGI
for gicv3.
And move the assertion from gic_it_raise_sgi() to
the caller function to improve the rea

driver: gic: support sgi raise for gicv3

Use write_icc_sgi1r() and write_icc_asgi1r() to raise SGI
for gicv3.
And move the assertion from gic_it_raise_sgi() to
the caller function to improve the readability
of gic_it_raise_sgi().

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add DEK blob support

The CAAM can generate a specific key blob called DEK blob - Data
Encryption Key blob. It encapsulates and encrypts the plain text key used
to encrypt the boot ima

drivers: caam: add DEK blob support

The CAAM can generate a specific key blob called DEK blob - Data
Encryption Key blob. It encapsulates and encrypts the plain text key used
to encrypt the boot image. This blob is decapsulated by the HAB - High
Assurance boot at boot to decrypt the boot image.

The DEK blob is a specific CAAM blob as it requires a header and the key
must be encapsulated from the CAAM secure memory.

Enable the CAAM DEK blob support on imx8m platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM secure memory driver

Add CAAM secure memory support. The CAAM secure memory is an embedded
memory within the CAAM used for data protection and special operations.

Enable the

drivers: caam: add CAAM secure memory driver

Add CAAM secure memory support. The CAAM secure memory is an embedded
memory within the CAAM used for data protection and special operations.

Enable the allocation of secure memory pages and partitions used by job
rings as input/output for special cryptographic operations.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add HAL for secure memory driver

Add hardware abstraction layer for CAAM secure memory registers. The
majority of the implementation is common to all i.MX platforms.
Only the secure m

drivers: caam: add HAL for secure memory driver

Add hardware abstraction layer for CAAM secure memory registers. The
majority of the implementation is common to all i.MX platforms.
Only the secure memory physical address retrieve method is platform
specific.
In this commit, this method is implemented for imx8m platforms only.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: check OPTEE DDR location if the CAAM DMA is 32 bits width

On i.MX platforms, the CAAM DMA width is limited to 32 bits. That
limitation requires OPTEE to be located in the 32 bits DDR

drivers: caam: check OPTEE DDR location if the CAAM DMA is 32 bits width

On i.MX platforms, the CAAM DMA width is limited to 32 bits. That
limitation requires OPTEE to be located in the 32 bits DDR address
space.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: avoid the assert failure when there's "assigned-clocks"

Once "assigned-clocks" is parsed correctly variable "clk" will
retain the non-NULL value and skip "return", when "res" is
non-ze

drivers: clk: avoid the assert failure when there's "assigned-clocks"

Once "assigned-clocks" is parsed correctly variable "clk" will
retain the non-NULL value and skip "return", when "res" is
non-zero for new "clock_idx" assert(false) will happen.

Signed-off-by: Tony Han <tony.han@microchip.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: remove dead code

Remove value check as it cannot be true and appears to be dead code.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@li

drivers: caam: remove dead code

Remove value check as it cannot be true and appears to be dead code.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: free resource upon sgtbuf initialization failure

Call caam_dmaobj_free() upon caam_dmaobj_input_sgtbuf() failure
to free buffer allocated by caam_dmaobj_input_sgtbuf().

Signed-off-b

drivers: caam: free resource upon sgtbuf initialization failure

Call caam_dmaobj_free() upon caam_dmaobj_input_sgtbuf() failure
to free buffer allocated by caam_dmaobj_input_sgtbuf().

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: plic: Refine interrupt targets from hartid to context

The PLIC specification says the interrupt targets are usually hart
contexts, where a hart context is a given privilege mode on a given

drivers: plic: Refine interrupt targets from hartid to context

The PLIC specification says the interrupt targets are usually hart
contexts, where a hart context is a given privilege mode on a given
hart. Therefore, PLIC driver should not only consider the HART ID, but
also current privilege mode. Refine it by introducing the function
called plic_get_context(), which translates the current HART ID into the
PLIC context ID. We assume that each hart has M-mode and S-mode,
therefore M-mode occupies even-numbered context ID, while S-mode
occupies odd-numbered context ID. The translation can be extended by
parsing device tree, submitted in future commits.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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drivers: caam: remove dead code

Remove value check as it cannot be true and appears to be dead code.
Use array index syntax instead of pointer arithmetic for better
readability.

Signed-off-by: Clem

drivers: caam: remove dead code

Remove value check as it cannot be true and appears to be dead code.
Use array index syntax instead of pointer arithmetic for better
readability.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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crypto: rsamgf: initialize allocated buffer

In drvcrypt_rsa_mgf1() function, the memcpy() could potentially
copy an uninitialized buffer. Allocate and initialize tmpdigest buffer
with calloc() inste

crypto: rsamgf: initialize allocated buffer

In drvcrypt_rsa_mgf1() function, the memcpy() could potentially
copy an uninitialized buffer. Allocate and initialize tmpdigest buffer
with calloc() instead of malloc().

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: mp: fix memory on CAAM descriptor allocation failure

Free the output DMA object upon CAAM descriptor allocation failure.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by

drivers: caam: mp: fix memory on CAAM descriptor allocation failure

Free the output DMA object upon CAAM descriptor allocation failure.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: free resource upon dmaobj initialization failure

Call caam_dmaobj_free() upon caam_dmaobj_init_[input|output}() failure
to free buffer allocated by allocate_private().

Signed-off-by:

drivers: caam: free resource upon dmaobj initialization failure

Call caam_dmaobj_free() upon caam_dmaobj_init_[input|output}() failure
to free buffer allocated by allocate_private().

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx_mu: read RX and TX buffer sizes from MU configuation register

On i.MX8ULP, there are multiple MUs with a different number of RX and TX
buffer sizes. To make the driver generic for all M

drivers: imx_mu: read RX and TX buffer sizes from MU configuation register

On i.MX8ULP, there are multiple MUs with a different number of RX and TX
buffer sizes. To make the driver generic for all MUs on this platform, get
the RX and TX buffer size from the MU configuration register.

The configuration remains static for i.MX8Q.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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crypto: stm32: use generic macro in authenc.c

Replace TOBE32 and FROMBE32 macros with generic TEE_U32_TO_BIG_ENDIAN and
TEE_U32_FROM_BIG_ENDIAN respectively.

Signed-off-by: Thomas Bourgoin <thomas.

crypto: stm32: use generic macro in authenc.c

Replace TOBE32 and FROMBE32 macros with generic TEE_U32_TO_BIG_ENDIAN and
TEE_U32_FROM_BIG_ENDIAN respectively.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_saes: redefine huk_subkey_derive()

We set huk_subkey_derive() as a weak function and we define it in SAES
driver to be able to use SAES IP to make a secure key derivation from
the SAE

drivers: stm32_saes: redefine huk_subkey_derive()

We set huk_subkey_derive() as a weak function and we define it in SAES
driver to be able to use SAES IP to make a secure key derivation from
the SAES only accessible SOC unique secret key.

We use the Key Derivation function (KDF) in counter mode defined in [1]
using as the PRF (pseudo random function) the PRF(AES-CMAC).
PRF(AES-CMAC) is hardware accelerated by SAES, and use the secure DHUK
(derived hardware unique key) only readable by the SAES IP.

Link: https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-108r1.pdf [1]
Co-developed-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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crypto: stm32: SAES cipher support

Add SAES HW driver, and update OP-TEE cipher hooks to be able to use
SAES or CRYP for cipher algorithms.
SAES and CRYP cannot be enabled at the same time in OP-TEE

crypto: stm32: SAES cipher support

Add SAES HW driver, and update OP-TEE cipher hooks to be able to use
SAES or CRYP for cipher algorithms.
SAES and CRYP cannot be enabled at the same time in OP-TEE.

Co-developed-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: crypto_api: fixes typo "bytes" to "bits"

Fixes a typo for *gen_keypair() in struct drvcrypt_ecc where the last
parameter was "size_bytes" while the value represents bits, so fix this by
renami

core: crypto_api: fixes typo "bytes" to "bits"

Fixes a typo for *gen_keypair() in struct drvcrypt_ecc where the last
parameter was "size_bytes" while the value represents bits, so fix this by
renaming it to "size_bits".

Fixes: d29cd2efcd46 ("core: driver: generic resources for crypto device driver - ECC")
Signed-off-by: Katsunori Kikuchi <Katsunori.Kikuchi@sony.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: fix to extract DH secret length from modulus

Prior to this patch, the DH secret, due to its mechanism, becomes a value
less than the key length of the Private key. Consequently, whe

drivers: crypto: fix to extract DH secret length from modulus

Prior to this patch, the DH secret, due to its mechanism, becomes a value
less than the key length of the Private key. Consequently, when obtaining
the maximum size of the secret from the current key length of the Public
key, the secret length falls short. So change this to extract DH secret
length from modulus instead of public key length.

Fixes: f6e2b9e2d1a2 ("drivers: crypto: implement crypto driver - DH")
Signed-off-by: Katsunori Kikuchi <Katsunori.Kikuchi@sony.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: drivers: ls_dspi: Make dspi_flush_fifo() static

Make dspi_flush_fifo() static as it gets exposed via ls_dspi_ops
structure.

Signed-off-by: Sriram Sriram <sriramsriram@microsoft.com>
Acked-by:

core: drivers: ls_dspi: Make dspi_flush_fifo() static

Make dspi_flush_fifo() static as it gets exposed via ls_dspi_ops
structure.

Signed-off-by: Sriram Sriram <sriramsriram@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: drivers: ls_dspi: Move SPI mode flag defines to header file

SPI mode flags are used by NXP SoC specific functions for MS PTA.

Signed-off-by: Sriram Sriram <sriramsriram@microsoft.com>
Acked-b

core: drivers: ls_dspi: Move SPI mode flag defines to header file

SPI mode flags are used by NXP SoC specific functions for MS PTA.

Signed-off-by: Sriram Sriram <sriramsriram@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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core: drivers: ls_dspi: Add flush DSPI module

Add flush DSPI module. This is called in ls_dspi_ops structure.

Signed-off-by: Carl Lamb <calamb@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklande

core: drivers: ls_dspi: Add flush DSPI module

Add flush DSPI module. This is called in ls_dspi_ops structure.

Signed-off-by: Carl Lamb <calamb@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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