| 9b72ef09 | 17-Nov-2023 |
loubaihui <loubaihui1@huawei.com> |
core: drivers: fix random number reading errors in hisi_trng
Fixes arguments passed to IO_READ32_POLL_TIMEOUT() macro and missing local variable definition in hisi_trng driver.
Fixes: fb5592f9cfeb
core: drivers: fix random number reading errors in hisi_trng
Fixes arguments passed to IO_READ32_POLL_TIMEOUT() macro and missing local variable definition in hisi_trng driver.
Fixes: fb5592f9cfeb ("core: drivers: add HiSilicon TRNG implementation") Signed-off-by: loubaihui <loubaihui1@huawei.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7d41fd4c | 13-Nov-2023 |
loubaihui <loubaihui1@huawei.com> |
core: drivers: modify debug and error messages in hisi_trng
Modify debug and error messages in hisi_trng.c
Fixes: fb5592f9cfeb ("core: drivers: add HiSilicon TRNG implementation") Signed-off-by: lo
core: drivers: modify debug and error messages in hisi_trng
Modify debug and error messages in hisi_trng.c
Fixes: fb5592f9cfeb ("core: drivers: add HiSilicon TRNG implementation") Signed-off-by: loubaihui <loubaihui1@huawei.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c7f9abce | 21-Nov-2023 |
Xiaoxu Zeng <zengxiaoxu@huawei.com> |
drivers: implement HiSilicon Queue Management (QM) module
The Hisilicon QM is a Queue Management module. In order to unify the interface between accelerator and software, a unified queue management
drivers: implement HiSilicon Queue Management (QM) module
The Hisilicon QM is a Queue Management module. In order to unify the interface between accelerator and software, a unified queue management module QM is used to interact with software. Each accelerator module integrates a QM. Software issues tasks to the SQ (Submmision Queue),and the QM obtains the address of the SQE (Submmision Queue Element). The BD (Buffer Description, same as SQE) information is sent to the accelerator. After the task processing is complete, the accelerator applies for a write-back address from the QM to write back the SQ.
Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 23f9bd99 | 02-Nov-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: IO domain regulators for STM32MP13
Add STM32MP13 IO domains regulators allowing a consumer to manage IO domains are voltage regulators.
Acked-by: Patrick Delaunay <patrick.delau
drivers: regulator: IO domain regulators for STM32MP13
Add STM32MP13 IO domains regulators allowing a consumer to manage IO domains are voltage regulators.
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Co-developed-by: Pascal Paillet <p.paillet@foss.st.com> Signed-off-by: Pascal Paillet <p.paillet@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 8c7282be | 10-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: gic: use DT bindings
Use DT bindings GIC_PPI and GIC_SIP instead of 1 and 0 raw values.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@li
drivers: gic: use DT bindings
Use DT bindings GIC_PPI and GIC_SIP instead of 1 and 0 raw values.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 14885eb1 | 05-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: gic: register to dt_driver
Registers GIC driver as an interrupt controller in DT_DRIVER providers when DT is supported. This change allows interrupt consumer nodes to leverage interrupts an
drivers: gic: register to dt_driver
Registers GIC driver as an interrupt controller in DT_DRIVER providers when DT is supported. This change allows interrupt consumer nodes to leverage interrupts and interrupts-extended properties DT bindings for their device drivers to retrieve their interrupts.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 33a0c835 | 14-Jun-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: interrupt: registering interrupt providers
Adds interrupt chip framework API functions for an interrupt controller to register as an interrupt provider in the driver probing sequence based on
core: interrupt: registering interrupt providers
Adds interrupt chip framework API functions for an interrupt controller to register as an interrupt provider in the driver probing sequence based on device tree. This allows interrupt consumer to be deferred when a dependent interrupt controller is not yet initialized.
Interrupt controllers register a driver in DT_DRIVER providers list with: interrupt_register_provider().
Interrupt consumer can get their interrupt through DT data with interrupt_dt_get(), interrupt_dt_get_by_index() or interrupt_dt_get_by_name().
This change removes inclusion of interrupt.h from kernel/dt.h as it is not needed and conflicts with inclusion of kernel/dt.h from kernel/interrupt.h.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| cd04d138 | 17-Nov-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: clk: print clock tree summary
Adds clk_print_summary() to print the clock tree current state on core console using the info trace level. Clock framework spinlock is help while clock tree is
drivers: clk: print clock tree summary
Adds clk_print_summary() to print the clock tree current state on core console using the info trace level. Clock framework spinlock is help while clock tree is printed.
The feature depends on CFG_DRIVERS_CLK_PRINT_TREE being enabled.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Co-developed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| bce2f88a | 19-Nov-2023 |
Vincent Mailhol <mailhol.vincent@wanadoo.fr> |
tree-wide: remove useless newline character in *MSG() messages
The *MSG() macros take care of printing a newline. Adding a newline character ('\n') is useless. Remove it.
Signed-off-by: Vincent Mai
tree-wide: remove useless newline character in *MSG() messages
The *MSG() macros take care of printing a newline. Adding a newline character ('\n') is useless. Remove it.
Signed-off-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f164f0f8 | 11-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: GPIO controlled regulator
Implements a GPIO controlled regulators driver compliant with DT nodes compatible with regulator-gpio. These regulators use GPIO pins to select the volt
drivers: regulator: GPIO controlled regulator
Implements a GPIO controlled regulators driver compliant with DT nodes compatible with regulator-gpio. These regulators use GPIO pins to select the voltage level. The implementation supports only dual voltage level selection using a single pin. The DT bindings allows more pins to select between more voltages but no known platform currently requires that so we preferred the simplified case.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ec740b9f | 23-Oct-2023 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: interrupt_raise_sgi() updates
Adds ITR_CPU_MASK_TO_THIS_CPU and ITR_CPU_MASK_TO_OTHER_CPUS to simplify targeting CPUs in some use cases. The cpu_mask parameter is changed to a uint32_t to make
core: interrupt_raise_sgi() updates
Adds ITR_CPU_MASK_TO_THIS_CPU and ITR_CPU_MASK_TO_OTHER_CPUS to simplify targeting CPUs in some use cases. The cpu_mask parameter is changed to a uint32_t to make room for the two new flags.
The gic driver is updated to support this new flag.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 0b1eafde | 07-Nov-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: crypto: caam: fix job ring interruption number
The job ring interruption number is 356 for job ring 3.
Fixes: b21f12209671 ("drivers: crypto: caam: use job ring 3 on i.mx8dxlevk") Signed-o
drivers: crypto: caam: fix job ring interruption number
The job ring interruption number is 356 for job ring 3.
Fixes: b21f12209671 ("drivers: crypto: caam: use job ring 3 on i.mx8dxlevk") Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| fb5592f9 | 09-Oct-2023 |
loubaihui <loubaihui1@huawei.com> |
core: drivers: add HiSilicon TRNG implementation
Based on HiSilicon hardware, a matching TRNG module is added. The driver is enabled for the D06 platform (PLATFORM=d06).
Signed-off-by: loubaihui <l
core: drivers: add HiSilicon TRNG implementation
Based on HiSilicon hardware, a matching TRNG module is added. The driver is enabled for the D06 platform (PLATFORM=d06).
Signed-off-by: loubaihui <loubaihui1@huawei.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Xiaoxu Zeng <zengxiaoxu@huawei.com> [jf: amend commit description] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| bd1fffe5 | 30-Oct-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
plat-stm32mp2: add new platform support
Initial configuration for STM32MP2x platforms. Add the initial memory layout and the MMU bus reference addresses. Default RAM size is 4GBytes It adds also the
plat-stm32mp2: add new platform support
Initial configuration for STM32MP2x platforms. Add the initial memory layout and the MMU bus reference addresses. Default RAM size is 4GBytes It adds also the console initialization and GIC support.
There are no shared resources on STM32MP25x platforms. Use stm32_pinctrl_set_secure_cfg() API in the STM32 UART driver for now.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 8370badb | 30-Oct-2023 |
Gatien Chevallier <gatien.chevallier@foss.st.com> |
drivers: stm32_gpio: remove unused APIs
Remove unused stm32_get_gpio_bank_offset() and stm32_get_gpio_count() APIs.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Eti
drivers: stm32_gpio: remove unused APIs
Remove unused stm32_get_gpio_bank_offset() and stm32_get_gpio_count() APIs.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b21f1220 | 02-Nov-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: crypto: caam: use job ring 3 on i.mx8dxlevk
Use the job ring #3 on i.mx8dxl to avoid resource conflict with other software stacks.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acke
drivers: crypto: caam: use job ring 3 on i.mx8dxlevk
Use the job ring #3 on i.mx8dxl to avoid resource conflict with other software stacks.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| c41ef459 | 23-Oct-2023 |
Alvin Chang <alvinga@andestech.com> |
drivers: plic: Ignore interrupt source ID 0
According to RISC-V PLIC specification, interrupt ID 0 is reserved to mean "no interrupt". Therefore, we should ignore it.
Signed-off-by: Alvin Chang <al
drivers: plic: Ignore interrupt source ID 0
According to RISC-V PLIC specification, interrupt ID 0 is reserved to mean "no interrupt". Therefore, we should ignore it.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 57fec118 | 16-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: atmel_piobu: upgrade to new interrupt framework
Moves atmel_piobu driver to the new interrupt framework API functions.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by
drivers: atmel_piobu: upgrade to new interrupt framework
Moves atmel_piobu driver to the new interrupt framework API functions.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| eb5b947d | 16-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: sp805_wdt.c: use the new interrupt API
Upgrades sp805_wdt.c driver to the new interrupt API functions as itr_alloc_add() and friends will be removed.
Reviewed-by: Jens Wiklander <jens.wikl
drivers: sp805_wdt.c: use the new interrupt API
Upgrades sp805_wdt.c driver to the new interrupt API functions as itr_alloc_add() and friends will be removed.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 297c6cbc | 16-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: crypto: caam: upgrade to new interrupt framework
Moves CAAM job ring driver to the new interrupt framework API functions.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off
drivers: crypto: caam: upgrade to new interrupt framework
Moves CAAM job ring driver to the new interrupt framework API functions.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c64c658b | 16-May-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: atmel_wdt: upgrade to new interrupt framework
Moves atmel_wdt watchdog driver to the new interrupt framework API functions.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-o
drivers: atmel_wdt: upgrade to new interrupt framework
Moves atmel_wdt watchdog driver to the new interrupt framework API functions.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| a20a065d | 17-Oct-2023 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: remove unnecessary header file
Remove #include <caam_utils_status.h>
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 8c49825d | 06-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
plat-stm32mp1: stm32mp1_pmic: regulators voltage list
Implements operator supported_voltages for stm32mp1 PMIC regulators driver. A voltage list array is allocated during initialization and freed up
plat-stm32mp1: stm32mp1_pmic: regulators voltage list
Implements operator supported_voltages for stm32mp1 PMIC regulators driver. A voltage list array is allocated during initialization and freed upon core initialization completion. This prevents wasting heap when the list is queried only during boot time.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 312d4476 | 07-Sep-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: regulator: stm32_vrefbuf
Implements and enable STM32 VREFBUF regulator driver for stm32mp1 platform.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carr
drivers: regulator: stm32_vrefbuf
Implements and enable STM32 VREFBUF regulator driver for stm32mp1 platform.
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| d5cb0882 | 13-Oct-2023 |
Etienne Carriere <etienne.carriere@foss.st.com> |
drivers: crypto: stm32: lower verbosity on SAES use
Changes SAES context allocation/release trace message from debug level to flow level otherwise each access to the secure storage emits debug messa
drivers: crypto: stm32: lower verbosity on SAES use
Changes SAES context allocation/release trace message from debug level to flow level otherwise each access to the secure storage emits debug messages.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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