driver: crypto: hisilicon: update qm init configs

1. add qm_disable_clock_gate for QM_HW_V3
2. set doorbell timeout to QM_DB_TIMEOUT_SET ns

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: J

driver: crypto: hisilicon: update qm init configs

1. add qm_disable_clock_gate for QM_HW_V3
2. set doorbell timeout to QM_DB_TIMEOUT_SET ns

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: caam: sm2 operation fallback

Fallback to software operations for SM2.

Reverts the temporary solution implemented in commit '3489781e9072
("drivers: caam: disable CFG_CRYPTO_SM2_* when ECC

drivers: caam: sm2 operation fallback

Fallback to software operations for SM2.

Reverts the temporary solution implemented in commit '3489781e9072
("drivers: caam: disable CFG_CRYPTO_SM2_* when ECC CAAM driver is
enabled")'.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

show more ...

drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms

The SECO firmware enables the RNG prediction resistance by default.
There is no need to read the CAAM RNG status registers.

Signe

drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms

The SECO firmware enables the RNG prediction resistance by default.
There is no need to read the CAAM RNG status registers.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

show more ...

drivers: stm32_rng: print RNG version at driver probe time

Print the RNG version that is read from RNG_VERR at driver probe time.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Re

drivers: stm32_rng: print RNG version at driver probe time

Print the RNG version that is read from RNG_VERR at driver probe time.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_rng: put max noise freq in compatible data

Define max noise clock frequency in the compatible data structure.
This avoids having configuration flags in the driver.

While there, updat

drivers: stm32_rng: put max noise freq in compatible data

Define max noise clock frequency in the compatible data structure.
This avoids having configuration flags in the driver.

While there, update STM32MP13/15 max RNG clock frequency to 48MHz
to align with latest certifications.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_rng: move RNG configuration to compat data

Register values cannot be part of the device tree.
As choosing another RNG configuration that is not the default
NIST-certified one should b

drivers: stm32_rng: move RNG configuration to compat data

Register values cannot be part of the device tree.
As choosing another RNG configuration that is not the default
NIST-certified one should be uncommon, it is acceptable to define
it in the compatible data and require to re-compile OP-TEE to change
the RNG configuration.

Also adds support for RNG V4.1 and above. These versions have a power
optimization and a modification of the seed error concealment. New
health tests and noise source registers are configurable and are part
of the RNG configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_rng: add stm32mp25 support

Add stm32mp25 platform support in stm32_rng driver.
On this platform, a security clock is shared between some hardware
blocks. For the RNG, it is the RNG ke

drivers: stm32_rng: add stm32mp25 support

Add stm32mp25 platform support in stm32_rng driver.
On this platform, a security clock is shared between some hardware
blocks. For the RNG, it is the RNG kernel clock. Therefore, the
clock gate is no more shared between the RNG bus and kernel clocks as
on STM32MP1x platforms and the bus clock has to be managed on its own.

Define the number of clock in the compatible data.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: sam: use header file "platform_config.h" instead of "sama5d2.h"

As "sama5d2.h" is included in "platform_config.h" it's better to use
"#include <platform_config.h>" for support more devices

drivers: sam: use header file "platform_config.h" instead of "sama5d2.h"

As "sama5d2.h" is included in "platform_config.h" it's better to use
"#include <platform_config.h>" for support more devices later.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

drivers: atmel_rtc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RTC is always secure for sama7g5 no need to configure
its security through matri

drivers: atmel_rtc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RTC is always secure for sama7g5 no need to configure
its security through matrix.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

show more ...

drivers: atmel_rstc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RSTC is always secure for sama7g5 no need to configure
its security through mat

drivers: atmel_rstc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RSTC is always secure for sama7g5 no need to configure
its security through matrix.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

show more ...

drivers: atmel_trng: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.w

drivers: atmel_trng: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

show more ...

drivers: atmel_piobu: update compatible with sama7g5

The number of tamper pins and some offsets of the registers are different
for sama7g5 and sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.c

drivers: atmel_piobu: update compatible with sama7g5

The number of tamper pins and some offsets of the registers are different
for sama7g5 and sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

show more ...

core: remove unnecessary includes

Remove unnecessary includes.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander

core: remove unnecessary includes

Remove unnecessary includes.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: scmi_msg: fix size_t trace format

Fix format specifier for size_t type argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@f

drivers: scmi_msg: fix size_t trace format

Fix format specifier for size_t type argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_i2c: fix header file inclusion order

Fix the order of header file inclusions.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carrier

drivers: stm32_i2c: fix header file inclusion order

Fix the order of header file inclusions.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

driver: i2c: stm32_i2c: fix call to stm32_i2c_init()

Fix call to stm32_i2c_init() that returns an int value, not a TEE_Result
code.

Fixes: 5bc9f8e5618b ("drivers: stm32_i2c: register a DT_DRIVER_I2

driver: i2c: stm32_i2c: fix call to stm32_i2c_init()

Fix call to stm32_i2c_init() that returns an int value, not a TEE_Result
code.

Fixes: 5bc9f8e5618b ("drivers: stm32_i2c: register a DT_DRIVER_I2C driver")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_i2c: apply pinctrl config at init

Add missing load of stm32_i2c pinctrl state at driver init.

Fixes: 73ba32eb0f6c ("drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL")
Reviewed-by: Gat

drivers: stm32_i2c: apply pinctrl config at init

Add missing load of stm32_i2c pinctrl state at driver init.

Fixes: 73ba32eb0f6c ("drivers: stm32_i2c: support CFG_DRIVERS_PINCTRL")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_i2c: analog filter config cannot fail

Local function i2c_config_analog_filter() cannot failed. Remove
useless test on bus state and useless return value.

Reviewed-by: Gatien Chevalli

drivers: stm32_i2c: analog filter config cannot fail

Local function i2c_config_analog_filter() cannot failed. Remove
useless test on bus state and useless return value.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: nvmem: add atmel_sfc driver

This driver handles the secure fuse controller that is present on the
sama5d2 series. It allows to read a 544 bits user defined area of fuses.
Content is exposed

drivers: nvmem: add atmel_sfc driver

This driver handles the secure fuse controller that is present on the
sama5d2 series. It allows to read a 544 bits user defined area of fuses.
Content is exposed through 17 32 bits registers. Rather than adding
complicated logic in atmel_sfc_read() for individual bytes, read all
the 16 registers at once (which are loaded at SoC startup from fuses)
and store them in an array convenient for copying from it to buffers.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: nvmem: add API for nvmem controllers

Add a nvmem API to access nvmem cells using device-tree description. This
API allows to register nvmeme provider and obtain nvmem cells for consumer.
Mu

drivers: nvmem: add API for nvmem controllers

Add a nvmem API to access nvmem cells using device-tree description. This
API allows to register nvmeme provider and obtain nvmem cells for consumer.
Much like other subsystem, this one relies on the generic dt_driver
mechanism.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: stm32_uart: fix incorrect USART_ISR_TXFE value

USART_ISR_TXFE indicates that the FIFO is empty. The register offset is
BIT(23), not BIT(27).

Signed-off-by: Gatien Chevallier <gatien.cheval

drivers: stm32_uart: fix incorrect USART_ISR_TXFE value

USART_ISR_TXFE indicates that the FIFO is empty. The register offset is
BIT(23), not BIT(27).

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: drivers: gpio: check return values from snprintf()

Check return values from snprintf().

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@fo

core: drivers: gpio: check return values from snprintf()

Check return values from snprintf().

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

driver: crypto: hisilicon: Fix temporary memory risk

When the mailbox operation times out, the software will
free the temporary memory. The hardware does not cancel
the mailbox operation and may con

driver: crypto: hisilicon: Fix temporary memory risk

When the mailbox operation times out, the software will
free the temporary memory. The hardware does not cancel
the mailbox operation and may continue to read and write
the free memory.
To solve the problem, we alloc buffer which has the same
lifecycle with qm.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

drivers: caam: Fix for TLS1.3 handshake failure

There is a limitation on some of i.MX8M series platforms.
When the input is marked as a hash value, it is moved first into
the Class 2 Context Registe

drivers: caam: Fix for TLS1.3 handshake failure

There is a limitation on some of i.MX8M series platforms.
When the input is marked as a hash value, it is moved first into
the Class 2 Context Register, which is only 40 bytes long.
From there, it is copied into the PKHA.
If HASH is more than 40bytes, extra bytes become zero, which is not
proper message representative,so signatures generation/verification
go wrong.

This makes a limitation when the hash size is longer than 40 bytes
and the signature component/private key size is longer than 40 bytes
As a workaround when the input is marked as a message representative,
then a different path is taken to bring the value into CAAM,
and the value stays intact.

CFG_NXP_CAAM_C2_CTX_REG_WA config flag is added to enable/disable
this workaround.
Currently it is enabled by default for i.MX8M platforms.

Fixes: 4b383f736e9e ("drivers: caam: implement NXP CAAM Driver - DSA")
Fixes: 503b5c013761 ("drivers: caam: implement NXP CAAM Driver - ECC")
Link: https://github.com/OP-TEE/optee_os/issues/6492
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

drivers: caam: add msg_type argument in DSA_SIGN/VERIFY macro

Add msg_type argument in DSA_SIGN/VERIFY macro.
Based on type of Message whether HASHED, Message representative, will
pass this argument

drivers: caam: add msg_type argument in DSA_SIGN/VERIFY macro

Add msg_type argument in DSA_SIGN/VERIFY macro.
Based on type of Message whether HASHED, Message representative, will
pass this argument.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...