core: pl011: implement rx_intr_{enable,disable}() callbacks

Implement the optional callbacks to enable and disable receive
interrupts from the PL011 UART. The receive timeout interrupt for the
UART

core: pl011: implement rx_intr_{enable,disable}() callbacks

Implement the optional callbacks to enable and disable receive
interrupts from the PL011 UART. The receive timeout interrupt for the
UART isn't used so don't enable it when initializing the UART.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: fix indentation in stm32mp13 clock driver

Fix indentation issues in STM32MP13 clock driver.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Ch

drivers: clk: fix indentation in stm32mp13 clock driver

Fix indentation issues in STM32MP13 clock driver.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: fix some stm32mp13 clock controls

Correct control field definitions for some STM32MP13 clock.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien

drivers: clk: fix some stm32mp13 clock controls

Correct control field definitions for some STM32MP13 clock.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: fix stm32mp13 RNG1 parent clock

Correct RNG1 clock parent list as LSE is not part of according to the
STM32MP13xx reference manual.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clock

drivers: clk: fix stm32mp13 RNG1 parent clock

Correct RNG1 clock parent list as LSE is not part of according to the
STM32MP13xx reference manual.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: list voltages controlled by a GPIO

Implement .supported_voltages() operation in regulator_gpio.c driver
to report voltage levels a level array that is required by scp-firmware
vo

drivers: regulator: list voltages controlled by a GPIO

Implement .supported_voltages() operation in regulator_gpio.c driver
to report voltage levels a level array that is required by scp-firmware
voltage domain module when a regulator-gpio is exposed through an
SCMI voltage domain. This change requires filed voltage_levels_uv[]
array of struct regulator_gpio to be sorted in increasing level value.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: hfic: fix HF_INTERRUPT HVC calls

The HF_INTERRUPT HVC calls has until now not been completely correct.
HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the
current CPU whil

core: hfic: fix HF_INTERRUPT HVC calls

The HF_INTERRUPT HVC calls has until now not been completely correct.
HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the
current CPU while HF_INTERRUPT_RECONFIGURE is used to globally enable a
physical interrupt. So update the HFIC callbacks accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: move hafnium.h into hfic.c

hafnium.h is only included from hfic.c so move the content into that
file instead. Comments trying to describe the paravirtualized interface
are removed and replaced

core: move hafnium.h into hfic.c

hafnium.h is only included from hfic.c so move the content into that
file instead. Comments trying to describe the paravirtualized interface
are removed and replaced by a link to official documentation.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_rstc: add the function to control sama7g5's USB reset

In sama7g5, USB POR is controlled by register RSTC_GRSTR.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fori

drivers: atmel_rstc: add the function to control sama7g5's USB reset

In sama7g5, USB POR is controlled by register RSTC_GRSTR.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_tcb: update to compatible with sama7g5

Update the clocks for sama7g5's TC.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
A

drivers: atmel_tcb: update to compatible with sama7g5

Update the clocks for sama7g5's TC.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_pio: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
Add configuration for PIOE as it is available for sama7g5.

Signed-off-by: Tony Han

drivers: atmel_pio: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
Add configuration for PIOE as it is available for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: atmel_shdwc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As SHDWC is always secure for sama7g5 no need to configure
its security through m

drivers: atmel_shdwc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As SHDWC is always secure for sama7g5 no need to configure
its security through matrix.
To process DDR controller for sama7g5 pm later.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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driver: crypto: hisilicon: update qm init configs

1. add qm_disable_clock_gate for QM_HW_V3
2. set doorbell timeout to QM_DB_TIMEOUT_SET ns

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: J

driver: crypto: hisilicon: update qm init configs

1. add qm_disable_clock_gate for QM_HW_V3
2. set doorbell timeout to QM_DB_TIMEOUT_SET ns

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: sm2 operation fallback

Fallback to software operations for SM2.

Reverts the temporary solution implemented in commit '3489781e9072
("drivers: caam: disable CFG_CRYPTO_SM2_* when ECC

drivers: caam: sm2 operation fallback

Fallback to software operations for SM2.

Reverts the temporary solution implemented in commit '3489781e9072
("drivers: caam: disable CFG_CRYPTO_SM2_* when ECC CAAM driver is
enabled")'.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms

The SECO firmware enables the RNG prediction resistance by default.
There is no need to read the CAAM RNG status registers.

Signe

drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms

The SECO firmware enables the RNG prediction resistance by default.
There is no need to read the CAAM RNG status registers.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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drivers: stm32_rng: print RNG version at driver probe time

Print the RNG version that is read from RNG_VERR at driver probe time.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Re

drivers: stm32_rng: print RNG version at driver probe time

Print the RNG version that is read from RNG_VERR at driver probe time.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: put max noise freq in compatible data

Define max noise clock frequency in the compatible data structure.
This avoids having configuration flags in the driver.

While there, updat

drivers: stm32_rng: put max noise freq in compatible data

Define max noise clock frequency in the compatible data structure.
This avoids having configuration flags in the driver.

While there, update STM32MP13/15 max RNG clock frequency to 48MHz
to align with latest certifications.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: move RNG configuration to compat data

Register values cannot be part of the device tree.
As choosing another RNG configuration that is not the default
NIST-certified one should b

drivers: stm32_rng: move RNG configuration to compat data

Register values cannot be part of the device tree.
As choosing another RNG configuration that is not the default
NIST-certified one should be uncommon, it is acceptable to define
it in the compatible data and require to re-compile OP-TEE to change
the RNG configuration.

Also adds support for RNG V4.1 and above. These versions have a power
optimization and a modification of the seed error concealment. New
health tests and noise source registers are configurable and are part
of the RNG configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rng: add stm32mp25 support

Add stm32mp25 platform support in stm32_rng driver.
On this platform, a security clock is shared between some hardware
blocks. For the RNG, it is the RNG ke

drivers: stm32_rng: add stm32mp25 support

Add stm32mp25 platform support in stm32_rng driver.
On this platform, a security clock is shared between some hardware
blocks. For the RNG, it is the RNG kernel clock. Therefore, the
clock gate is no more shared between the RNG bus and kernel clocks as
on STM32MP1x platforms and the bus clock has to be managed on its own.

Define the number of clock in the compatible data.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: sam: use header file "platform_config.h" instead of "sama5d2.h"

As "sama5d2.h" is included in "platform_config.h" it's better to use
"#include <platform_config.h>" for support more devices

drivers: sam: use header file "platform_config.h" instead of "sama5d2.h"

As "sama5d2.h" is included in "platform_config.h" it's better to use
"#include <platform_config.h>" for support more devices later.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: atmel_rtc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RTC is always secure for sama7g5 no need to configure
its security through matri

drivers: atmel_rtc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RTC is always secure for sama7g5 no need to configure
its security through matrix.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

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drivers: atmel_rstc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RSTC is always secure for sama7g5 no need to configure
its security through mat

drivers: atmel_rstc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As RSTC is always secure for sama7g5 no need to configure
its security through matrix.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

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drivers: atmel_trng: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.w

drivers: atmel_trng: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

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drivers: atmel_piobu: update compatible with sama7g5

The number of tamper pins and some offsets of the registers are different
for sama7g5 and sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.c

drivers: atmel_piobu: update compatible with sama7g5

The number of tamper pins and some offsets of the registers are different
for sama7g5 and sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Akshay Bhat <akshay.bhat@timesys.com>

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core: remove unnecessary includes

Remove unnecessary includes.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander

core: remove unnecessary includes

Remove unnecessary includes.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: scmi_msg: fix size_t trace format

Fix format specifier for size_t type argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@f

drivers: scmi_msg: fix size_t trace format

Fix format specifier for size_t type argument.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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