drivers: add stm32 RIFSC support

Add the RIFSC new driver support.

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed

drivers: add stm32 RIFSC support

Add the RIFSC new driver support.

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.

This driver parses the RIFSC device tree configuration and applies
it to put the firewall in place. Therefore, the device tree is
mandatory.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: firewall: add stm32_rif driver for common RIF features

The resource isolation framework (RIF) is a comprehensive set of
hardware blocks designed to enforce and manage the isolation of
STM32

drivers: firewall: add stm32_rif driver for common RIF features

The resource isolation framework (RIF) is a comprehensive set of
hardware blocks designed to enforce and manage the isolation of
STM32MP25xx hardware resources, like memories and peripherals.

The RIF manages security and privilege levels as well as compartment
filtering. Each compartment is identified by a Compartment ID (CID).

Therefore, the access filtering can be, depending on the case:
• restricted to none, one or more than one CID
• secure-only, non-secure only, or both
• privileged-only or privileged/unprivileged
• read-only, write-only, or read/write

Add a firewall driver folder that contains firewall drivers.
This RIF driver contains generic features shared between all drivers
managing RIF configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: crypto: stm32_saes: fallback to software on 192bit AES keys

Implement AES software operation for 192 bits keys as these are not
supported by the STM32 SAES peripheral. For that purpose ciph

drivers: crypto: stm32_saes: fallback to software on 192bit AES keys

Implement AES software operation for 192 bits keys as these are not
supported by the STM32 SAES peripheral. For that purpose ciphering final,
context copy and context freeing operations common functions are split
into CRYP/SAES peripheral specific functions.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: crypto: stm32: cleanup cipher operation structure

Move cryp_ops definition in the source file to have it defined right
next to the CRYP ciphering operation handlers.

Add missing static key

drivers: crypto: stm32: cleanup cipher operation structure

Move cryp_ops definition in the source file to have it defined right
next to the CRYP ciphering operation handlers.

Add missing static keyword in CRYP and SAES operation handlers
structures that are local to the source file.

No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: crypto: stm32: move context allocation/free functions

Move cipher context allocation and free functions to place them
next to each other for CRYP and SAES support to ease their maintenance

drivers: crypto: stm32: move context allocation/free functions

Move cipher context allocation and free functions to place them
next to each other for CRYP and SAES support to ease their maintenance
as the context free sequence is the counter part of the context
allocation sequence. No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss

drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: clk: sam: update to support slow clock for sama7g5

Add CLK_DT_DECLARE for sama7g5's slow clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissie

drivers: clk: sam: update to support slow clock for sama7g5

Add CLK_DT_DECLARE for sama7g5's slow clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: clk: sam: add PMC definitions for sama7g5

Add PMC definitions to "at91_pmc.h" for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

drivers: clk: sam: add PMC definitions for sama7g5

Add PMC definitions to "at91_pmc.h" for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: clk: sam: add UTMI clocks for sama7g5 USB PHY

Add functions for configuring UTMI clocks for sama7g5 USB PHY.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <je

drivers: clk: sam: add UTMI clocks for sama7g5 USB PHY

Add functions for configuring UTMI clocks for sama7g5 USB PHY.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: clk: sam: update UTMI clock for sama7g5

The frequency of the parent clock for UTMI is different with sama5d2.
The control of UTMI clock is different with sama5d2.

Signed-off-by: Tony Han <

drivers: clk: sam: update UTMI clock for sama7g5

The frequency of the parent clock for UTMI is different with sama5d2.
The control of UTMI clock is different with sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

driver: crypto: hisilicon: fix error handling

When qm_set_vft_common() fails to configure, qm_set_xqc_vft() is
called with the num argument as zero to disable the device. Update
qm_set_xqc_vft() to

driver: crypto: hisilicon: fix error handling

When qm_set_vft_common() fails to configure, qm_set_xqc_vft() is
called with the num argument as zero to disable the device. Update
qm_set_xqc_vft() to handle this error path.

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: se050: fix default configuration for the SE applet

Invalid character was merged in the fixed commit.

Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet")
Sig

drivers: se050: fix default configuration for the SE applet

Invalid character was merged in the fixed commit.

Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet")
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: pta: widevine: Add the init implementation

On the new ChromeOS mediatek platform, we will use the device tree to
pass hardware unique key and the parameters for widevine TAs.

Signed-off-by: Y

core: pta: widevine: Add the init implementation

On the new ChromeOS mediatek platform, we will use the device tree to
pass hardware unique key and the parameters for widevine TAs.

Signed-off-by: Yi Chou <yich@google.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests i

drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests involve only the software key selection
(_SAES_CR_KEYSEL_SOFT) which value is 0 and matches the SoC default
key selection register value.

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: pl011: implement rx_intr_{enable,disable}() callbacks

Implement the optional callbacks to enable and disable receive
interrupts from the PL011 UART. The receive timeout interrupt for the
UART

core: pl011: implement rx_intr_{enable,disable}() callbacks

Implement the optional callbacks to enable and disable receive
interrupts from the PL011 UART. The receive timeout interrupt for the
UART isn't used so don't enable it when initializing the UART.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

drivers: clk: fix indentation in stm32mp13 clock driver

Fix indentation issues in STM32MP13 clock driver.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Ch

drivers: clk: fix indentation in stm32mp13 clock driver

Fix indentation issues in STM32MP13 clock driver.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: clk: fix some stm32mp13 clock controls

Correct control field definitions for some STM32MP13 clock.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien

drivers: clk: fix some stm32mp13 clock controls

Correct control field definitions for some STM32MP13 clock.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: clk: fix stm32mp13 RNG1 parent clock

Correct RNG1 clock parent list as LSE is not part of according to the
STM32MP13xx reference manual.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clock

drivers: clk: fix stm32mp13 RNG1 parent clock

Correct RNG1 clock parent list as LSE is not part of according to the
STM32MP13xx reference manual.

Fixes: 5436921f6866 ("clk: stm32mp13: add all clocks for STM32MP13")
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: regulator: list voltages controlled by a GPIO

Implement .supported_voltages() operation in regulator_gpio.c driver
to report voltage levels a level array that is required by scp-firmware
vo

drivers: regulator: list voltages controlled by a GPIO

Implement .supported_voltages() operation in regulator_gpio.c driver
to report voltage levels a level array that is required by scp-firmware
voltage domain module when a regulator-gpio is exposed through an
SCMI voltage domain. This change requires filed voltage_levels_uv[]
array of struct regulator_gpio to be sorted in increasing level value.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: hfic: fix HF_INTERRUPT HVC calls

The HF_INTERRUPT HVC calls has until now not been completely correct.
HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the
current CPU whil

core: hfic: fix HF_INTERRUPT HVC calls

The HF_INTERRUPT HVC calls has until now not been completely correct.
HF_INTERRUPT_ENABLE is used to enable/disable a virtual interrupt on the
current CPU while HF_INTERRUPT_RECONFIGURE is used to globally enable a
physical interrupt. So update the HFIC callbacks accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: move hafnium.h into hfic.c

hafnium.h is only included from hfic.c so move the content into that
file instead. Comments trying to describe the paravirtualized interface
are removed and replaced

core: move hafnium.h into hfic.c

hafnium.h is only included from hfic.c so move the content into that
file instead. Comments trying to describe the paravirtualized interface
are removed and replaced by a link to official documentation.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: atmel_rstc: add the function to control sama7g5's USB reset

In sama7g5, USB POR is controlled by register RSTC_GRSTR.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fori

drivers: atmel_rstc: add the function to control sama7g5's USB reset

In sama7g5, USB POR is controlled by register RSTC_GRSTR.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: atmel_tcb: update to compatible with sama7g5

Update the clocks for sama7g5's TC.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
A

drivers: atmel_tcb: update to compatible with sama7g5

Update the clocks for sama7g5's TC.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: atmel_pio: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
Add configuration for PIOE as it is available for sama7g5.

Signed-off-by: Tony Han

drivers: atmel_pio: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
Add configuration for PIOE as it is available for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: atmel_shdwc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As SHDWC is always secure for sama7g5 no need to configure
its security through m

drivers: atmel_shdwc: update to compatible with sama7g5

Add the compatible string to device match table for sama7g5.
As SHDWC is always secure for sama7g5 no need to configure
its security through matrix.
To process DDR controller for sama7g5 pm later.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...