1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2022-2024, STMicroelectronics 4 */ 5 6 #ifndef __DRIVERS_STM32_RIF_H 7 #define __DRIVERS_STM32_RIF_H 8 9 #include <dt-bindings/firewall/stm32mp25-rif.h> 10 #include <tee_api_types.h> 11 #include <types_ext.h> 12 #include <util.h> 13 14 /* 15 * CIDCFGR register 16 */ 17 #define _CIDCFGR_CFEN BIT(0) 18 #define _CIDCFGR_SEMEN BIT(1) 19 #define _CIDCFGR_SEMWL(x) BIT(SEMWL_SHIFT + (x)) 20 21 /* 22 * SEMCR register 23 */ 24 #define _SEMCR_MUTEX BIT(0) 25 #define _SEMCR_SEMCID_SHIFT U(4) 26 #define _SEMCR_SEMCID_MASK GENMASK_32(6, 4) 27 28 /* 29 * Miscellaneous 30 */ 31 #define MAX_CID_SUPPORTED U(8) 32 33 #define SCID_SHIFT U(4) 34 #define SEMWL_SHIFT U(16) 35 #define RIF_ID_SHIFT U(24) 36 37 #define RIF_ID_MASK GENMASK_32(31, 24) 38 #define RIF_CHANNEL_ID(x) ((RIF_ID_MASK & (x)) >> RIF_ID_SHIFT) 39 40 #define RIFPROT_SEC BIT(8) 41 #define RIFPROT_PRIV BIT(9) 42 #define RIFPROT_LOCK BIT(10) 43 44 /** 45 * struct rif_conf_data - Structure containing RIF configuration data 46 * 47 * @access_mask: Array of the masks of the registers which will be configured. 48 * @sec_conf: Secure configuration registers. 49 * @priv_conf: Privilege configuration registers. 50 * @cid_confs: CID filtering configuration register value for a peripheral 51 * resource (e.g: GPIO pins, FMC controllers) 52 * @lock_conf: RIF configuration locking registers 53 * 54 * For a hardware block having 56 channels, there will be 56 cid_confs 55 * registers and 2 sec_conf and priv_conf registers 56 */ 57 struct rif_conf_data { 58 uint32_t *access_mask; 59 uint32_t *sec_conf; 60 uint32_t *priv_conf; 61 uint32_t *cid_confs; 62 uint32_t *lock_conf; 63 }; 64 65 #ifdef CFG_STM32_RIF 66 /** 67 * stm32_rif_scid_ok() - Check if a given static CID configuration authorizes 68 * access to a given CID 69 * 70 * @cidcfgr: Value of the CIDCFGR register 71 * @scid_m: Mask of the static CID in the register 72 * @cid_to_check: CID of the target compartment 73 * 74 * Returns true if given CID is authorized, false otherwise. 75 */ 76 static inline bool stm32_rif_scid_ok(uint32_t cidcfgr, uint32_t scid_m, 77 uint32_t cid_to_check) 78 { 79 return (cidcfgr & scid_m) == SHIFT_U32(cid_to_check, SCID_SHIFT) && 80 !(cidcfgr & _CIDCFGR_SEMEN); 81 } 82 83 /** 84 * stm32_rif_semaphore_enabled_and_ok() - Check if semaphore mode is enabled and 85 * that a given CID can request the 86 * semaphore ownership 87 * 88 * @cidcfgr: Value of the cidcfgr register 89 * @cid_bf_to_check: Bitfield of CIDs to check 90 * 91 * Returns true if all requested CIDs can request the semaphore ownership, 92 * false otherwise. 93 */ 94 static inline bool stm32_rif_semaphore_enabled_and_ok(uint32_t cidcfgr, 95 uint32_t cid_bf_to_check) 96 { 97 return (cidcfgr & _CIDCFGR_CFEN) && (cidcfgr & _CIDCFGR_SEMEN) && 98 (cidcfgr & _CIDCFGR_SEMWL(cid_bf_to_check)); 99 } 100 101 /** 102 * stm32_rif_check_access() - Test peripheral access for a given compartment 103 * 104 * @cidcfgr: CIDCFGR configuration register value 105 * @semcr: SEMCR register value 106 * @nb_cid_supp: Number of supported CID for the peripheral 107 * @cid_to_check: CID of the target compartment 108 * 109 * Returns TEE_SUCCESS if access is authorized, a TEE_Result error value 110 * otherwise. 111 */ 112 TEE_Result stm32_rif_check_access(uint32_t cidcfgr, 113 uint32_t semcr, 114 unsigned int nb_cid_supp, 115 unsigned int cid_to_check); 116 117 /** 118 * stm32_rif_parse_cfg() - Parse RIF config from Device Tree extracted 119 * information 120 * 121 * @rif_conf: Configuration read in the device tree 122 * @conf_data: Buffer containing the RIF configuration to apply for a peripheral 123 * @nb_cid_supp: Number of supported CID for the peripheral 124 * @nb_channel: Number of channels for the peripheral 125 */ 126 void stm32_rif_parse_cfg(uint32_t rif_conf, 127 struct rif_conf_data *conf_data, 128 unsigned int nb_cid_supp, 129 unsigned int nb_channel); 130 131 /** 132 * stm32_rif_semaphore_is_available() - Checks if the _SEMCR_MUTEX bit is set 133 * 134 * @addr: Address of the register to read from 135 */ 136 bool stm32_rif_semaphore_is_available(vaddr_t addr); 137 138 /** 139 * stm32_rif_semaphore_is_available() - Acquires the semaphore by setting the 140 * _SEMCR_MUTEX bit 141 * 142 * @addr: Address of the register to write to 143 * @nb_cid_supp: Number of CID supported 144 */ 145 TEE_Result stm32_rif_acquire_semaphore(vaddr_t addr, 146 unsigned int nb_cid_supp); 147 148 /** 149 * stm32_rif_semaphore_is_available() - Releases the semaphore by clearing the 150 * _SEMCR_MUTEX bit 151 * 152 * @addr: Address of the register to write to 153 * @nb_cid_supp: Number of CID supported 154 */ 155 TEE_Result stm32_rif_release_semaphore(vaddr_t addr, 156 unsigned int nb_cid_supp); 157 #else 158 static inline bool stm32_rif_scid_ok(uint32_t cidcfgr, uint32_t scid_m, 159 uint32_t cid_to_check) 160 { 161 return true; 162 } 163 164 static inline bool stm32_rif_semaphore_enabled_and_ok(uint32_t cidcfgr, 165 uint32_t cid_bf_to_check) 166 { 167 return true; 168 } 169 170 static inline TEE_Result 171 stm32_rif_check_access(uint32_t cidcfgr __unused, 172 uint32_t semcr __unused, 173 unsigned int nb_cid_supp __unused, 174 unsigned int cid_to_check __unused) 175 { 176 return TEE_SUCCESS; 177 } 178 179 static inline void 180 stm32_rif_parse_cfg(uint32_t rif_conf __unused, 181 struct rif_conf_data *conf_data __unused, 182 unsigned int nb_cid_supp __unused, 183 unsigned int nb_channel __unused) 184 { 185 } 186 187 static inline bool stm32_rif_semaphore_is_available(vaddr_t addr __unused) 188 { 189 return true; 190 } 191 192 static inline TEE_Result 193 stm32_rif_acquire_semaphore(vaddr_t addr __unused, 194 unsigned int nb_cid_supp __unused) 195 { 196 return TEE_SUCCESS; 197 } 198 199 static inline TEE_Result 200 stm32_rif_release_semaphore(vaddr_t addr __unused, 201 unsigned int nb_cid_supp __unused) 202 { 203 return TEE_SUCCESS; 204 } 205 #endif /* CFG_STM32_RIF */ 206 #endif /* __DRIVERS_STM32_RIF_H */ 207