drivers: clk: clk-stm32mp13: round up VCO to the nearest frequency

Round up the vco clock to avoid unexpected clock rate:
- 999,999,023 Hz instead 1,000,000,000 Hz
- 417,755,859 Hz instead 417,800,0

drivers: clk: clk-stm32mp13: round up VCO to the nearest frequency

Round up the vco clock to avoid unexpected clock rate:
- 999,999,023 Hz instead 1,000,000,000 Hz
- 417,755,859 Hz instead 417,800,000 Hz

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired

If an oscillator is not wired we shouldn't gate it to avoid a panic.
For example the external LSE oscillator may not be supported

drivers: clk: clk-stm32mp13: don't gate/ungate oscillators not wired

If an oscillator is not wired we shouldn't gate it to avoid a panic.
For example the external LSE oscillator may not be supported on a board
in which case node named clk-lse is disabled in the board DTS file.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: clk-stm32mp13: add ADC and SPI clocks

Add definition of ADCs and SPI buses clocks for platform variant
STM32MP13.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed

drivers: clk: clk-stm32mp13: add ADC and SPI clocks

Add definition of ADCs and SPI buses clocks for platform variant
STM32MP13.

Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: add CAAM key support for DH

Add CAAM key support for DH.
Add DH black key support for shared secret generation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sa

drivers: caam: add CAAM key support for DH

Add CAAM key support for DH.
Add DH black key support for shared secret generation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for ECC

Add CAAM key support for ECC.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for ECC

Add CAAM key support for ECC.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for DSA

Add CAAM key support for DSA.
Add DSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for DSA

Add CAAM key support for DSA.
Add DSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key support for RSA

Add CAAM key support for RSA.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@n

drivers: caam: add CAAM key support for RSA

Add CAAM key support for RSA.
Add RSA black key support for key pair generation and sign/decrypt
functions.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: add CAAM key driver

Add CAAM key driver and CAAM key object.
Add key blob encapsulation methods.
Add key serialize and deserialize functions for bignum encapsulation.

Signed-off-by:

drivers: caam: add CAAM key driver

Add CAAM key driver and CAAM key object.
Add key blob encapsulation methods.
Add key serialize and deserialize functions for bignum encapsulation.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: fix DSA_DUMPDESC macro

Fix typo in DSA_DUMPDESC and replace MP_TRACE with DSA_TRACE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier

drivers: caam: fix DSA_DUMPDESC macro

Fix typo in DSA_DUMPDESC and replace MP_TRACE with DSA_TRACE.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: add missing header

Add missing caam_status.h include.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: caam: add class field to FIFO_ST macro

Add class field to FIFO_ST macro and update existing
usage of FIFO_ST with required CLASS.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Sig

drivers: caam: add class field to FIFO_ST macro

Add class field to FIFO_ST macro and update existing
usage of FIFO_ST with required CLASS.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: add stm32 RIFSC support

Add the RIFSC new driver support.

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed

drivers: add stm32 RIFSC support

Add the RIFSC new driver support.

RIFSC (RIF Security Controller) is responsible for the isolation
of hardware resources like memory or peripherals. It is composed of:

-RISC registers(slave peripherals) with RISUP(Resource Isolation
Slave Unit for Peripherals) OR RISAL(Resource Isolation Slave Unit
for Address space - Lite) logics.
-RIMC registers(Non RIF-Aware masters counterpart) with RIMU
(Resource Isolation Master Unit) logic. It is possible for a master to
inherit from its slave port(RISUP) configuration.

This driver parses the RIFSC device tree configuration and applies
it to put the firewall in place. Therefore, the device tree is
mandatory.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: firewall: add stm32_rif driver for common RIF features

The resource isolation framework (RIF) is a comprehensive set of
hardware blocks designed to enforce and manage the isolation of
STM32

drivers: firewall: add stm32_rif driver for common RIF features

The resource isolation framework (RIF) is a comprehensive set of
hardware blocks designed to enforce and manage the isolation of
STM32MP25xx hardware resources, like memories and peripherals.

The RIF manages security and privilege levels as well as compartment
filtering. Each compartment is identified by a Compartment ID (CID).

Therefore, the access filtering can be, depending on the case:
• restricted to none, one or more than one CID
• secure-only, non-secure only, or both
• privileged-only or privileged/unprivileged
• read-only, write-only, or read/write

Add a firewall driver folder that contains firewall drivers.
This RIF driver contains generic features shared between all drivers
managing RIF configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_saes: fallback to software on 192bit AES keys

Implement AES software operation for 192 bits keys as these are not
supported by the STM32 SAES peripheral. For that purpose ciph

drivers: crypto: stm32_saes: fallback to software on 192bit AES keys

Implement AES software operation for 192 bits keys as these are not
supported by the STM32 SAES peripheral. For that purpose ciphering final,
context copy and context freeing operations common functions are split
into CRYP/SAES peripheral specific functions.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32: cleanup cipher operation structure

Move cryp_ops definition in the source file to have it defined right
next to the CRYP ciphering operation handlers.

Add missing static key

drivers: crypto: stm32: cleanup cipher operation structure

Move cryp_ops definition in the source file to have it defined right
next to the CRYP ciphering operation handlers.

Add missing static keyword in CRYP and SAES operation handlers
structures that are local to the source file.

No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32: move context allocation/free functions

Move cipher context allocation and free functions to place them
next to each other for CRYP and SAES support to ease their maintenance

drivers: crypto: stm32: move context allocation/free functions

Move cipher context allocation and free functions to place them
next to each other for CRYP and SAES support to ease their maintenance
as the context free sequence is the counter part of the context
allocation sequence. No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss

drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support slow clock for sama7g5

Add CLK_DT_DECLARE for sama7g5's slow clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissie

drivers: clk: sam: update to support slow clock for sama7g5

Add CLK_DT_DECLARE for sama7g5's slow clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add PMC definitions for sama7g5

Add PMC definitions to "at91_pmc.h" for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

drivers: clk: sam: add PMC definitions for sama7g5

Add PMC definitions to "at91_pmc.h" for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add UTMI clocks for sama7g5 USB PHY

Add functions for configuring UTMI clocks for sama7g5 USB PHY.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <je

drivers: clk: sam: add UTMI clocks for sama7g5 USB PHY

Add functions for configuring UTMI clocks for sama7g5 USB PHY.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update UTMI clock for sama7g5

The frequency of the parent clock for UTMI is different with sama5d2.
The control of UTMI clock is different with sama5d2.

Signed-off-by: Tony Han <

drivers: clk: sam: update UTMI clock for sama7g5

The frequency of the parent clock for UTMI is different with sama5d2.
The control of UTMI clock is different with sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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driver: crypto: hisilicon: fix error handling

When qm_set_vft_common() fails to configure, qm_set_xqc_vft() is
called with the num argument as zero to disable the device. Update
qm_set_xqc_vft() to

driver: crypto: hisilicon: fix error handling

When qm_set_vft_common() fails to configure, qm_set_xqc_vft() is
called with the num argument as zero to disable the device. Update
qm_set_xqc_vft() to handle this error path.

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: se050: fix default configuration for the SE applet

Invalid character was merged in the fixed commit.

Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet")
Sig

drivers: se050: fix default configuration for the SE applet

Invalid character was merged in the fixed commit.

Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet")
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: pta: widevine: Add the init implementation

On the new ChromeOS mediatek platform, we will use the device tree to
pass hardware unique key and the parameters for widevine TAs.

Signed-off-by: Y

core: pta: widevine: Add the init implementation

On the new ChromeOS mediatek platform, we will use the device tree to
pass hardware unique key and the parameters for widevine TAs.

Signed-off-by: Yi Chou <yich@google.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests i

drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests involve only the software key selection
(_SAES_CR_KEYSEL_SOFT) which value is 0 and matches the SoC default
key selection register value.

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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