1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021, Bootlin 4 * Copyright (c) 2023, STMicroelectronics 5 */ 6 7 #include <config.h> 8 #include <drivers/clk.h> 9 #include <kernel/boot.h> 10 #include <kernel/panic.h> 11 #include <kernel/spinlock.h> 12 #include <malloc.h> 13 #include <stddef.h> 14 #include <stdio.h> 15 16 /* Global clock tree lock */ 17 static unsigned int clk_lock = SPINLOCK_UNLOCK; 18 19 #ifdef CFG_DRIVERS_CLK_PRINT_TREE 20 static SLIST_HEAD(, clk) clock_list = SLIST_HEAD_INITIALIZER(clock_list); 21 #endif 22 23 struct clk *clk_alloc(const char *name, const struct clk_ops *ops, 24 struct clk **parent_clks, size_t parent_count) 25 { 26 struct clk *clk = NULL; 27 size_t parent = 0; 28 29 clk = calloc(1, sizeof(*clk) + parent_count * sizeof(clk)); 30 if (!clk) 31 return NULL; 32 33 clk->num_parents = parent_count; 34 for (parent = 0; parent < parent_count; parent++) 35 clk->parents[parent] = parent_clks[parent]; 36 37 clk->name = name; 38 clk->ops = ops; 39 refcount_set(&clk->enabled_count, 0); 40 41 return clk; 42 } 43 44 void clk_free(struct clk *clk) 45 { 46 free(clk); 47 } 48 49 static bool __maybe_unused clk_check(struct clk *clk) 50 { 51 if (!clk || !clk->ops) 52 return false; 53 54 if (clk->ops->set_parent && !clk->ops->get_parent) 55 return false; 56 57 if (clk->num_parents > 1 && !clk->ops->get_parent) 58 return false; 59 60 return true; 61 } 62 63 static void clk_compute_rate_no_lock(struct clk *clk) 64 { 65 unsigned long parent_rate = 0; 66 67 if (clk->parent) 68 parent_rate = clk->parent->rate; 69 70 if (clk->ops->get_rate) 71 clk->rate = clk->ops->get_rate(clk, parent_rate); 72 else 73 clk->rate = parent_rate; 74 } 75 76 struct clk *clk_get_parent_by_index(struct clk *clk, size_t pidx) 77 { 78 if (pidx >= clk->num_parents) 79 return NULL; 80 81 return clk->parents[pidx]; 82 } 83 84 static void clk_init_parent(struct clk *clk) 85 { 86 size_t pidx = 0; 87 88 switch (clk->num_parents) { 89 case 0: 90 break; 91 case 1: 92 clk->parent = clk->parents[0]; 93 break; 94 default: 95 pidx = clk->ops->get_parent(clk); 96 assert(pidx < clk->num_parents); 97 98 clk->parent = clk->parents[pidx]; 99 break; 100 } 101 } 102 103 TEE_Result clk_register(struct clk *clk) 104 { 105 assert(clk_check(clk)); 106 107 clk_init_parent(clk); 108 clk_compute_rate_no_lock(clk); 109 110 #ifdef CFG_DRIVERS_CLK_PRINT_TREE 111 SLIST_INSERT_HEAD(&clock_list, clk, link); 112 #endif 113 114 DMSG("Registered clock %s, freq %lu", clk->name, clk_get_rate(clk)); 115 116 return TEE_SUCCESS; 117 } 118 119 static bool clk_is_enabled_no_lock(struct clk *clk) 120 { 121 return refcount_val(&clk->enabled_count) != 0; 122 } 123 124 bool clk_is_enabled(struct clk *clk) 125 { 126 return clk_is_enabled_no_lock(clk); 127 } 128 129 static void clk_disable_no_lock(struct clk *clk) 130 { 131 struct clk *parent = NULL; 132 133 if (!refcount_dec(&clk->enabled_count)) 134 return; 135 136 if (clk->ops->disable) 137 clk->ops->disable(clk); 138 139 parent = clk_get_parent(clk); 140 if (parent) 141 clk_disable_no_lock(parent); 142 } 143 144 static TEE_Result clk_enable_no_lock(struct clk *clk) 145 { 146 TEE_Result res = TEE_ERROR_GENERIC; 147 struct clk *parent = NULL; 148 149 if (refcount_inc(&clk->enabled_count)) 150 return TEE_SUCCESS; 151 152 parent = clk_get_parent(clk); 153 if (parent) { 154 res = clk_enable_no_lock(parent); 155 if (res) 156 return res; 157 } 158 159 if (clk->ops->enable) { 160 res = clk->ops->enable(clk); 161 if (res) { 162 if (parent) 163 clk_disable_no_lock(parent); 164 165 return res; 166 } 167 } 168 169 refcount_set(&clk->enabled_count, 1); 170 171 return TEE_SUCCESS; 172 } 173 174 TEE_Result clk_enable(struct clk *clk) 175 { 176 uint32_t exceptions = 0; 177 TEE_Result res = TEE_ERROR_GENERIC; 178 179 exceptions = cpu_spin_lock_xsave(&clk_lock); 180 res = clk_enable_no_lock(clk); 181 cpu_spin_unlock_xrestore(&clk_lock, exceptions); 182 183 return res; 184 } 185 186 void clk_disable(struct clk *clk) 187 { 188 uint32_t exceptions = 0; 189 190 exceptions = cpu_spin_lock_xsave(&clk_lock); 191 clk_disable_no_lock(clk); 192 cpu_spin_unlock_xrestore(&clk_lock, exceptions); 193 } 194 195 unsigned long clk_get_rate(struct clk *clk) 196 { 197 return clk->rate; 198 } 199 200 static TEE_Result clk_set_rate_no_lock(struct clk *clk, unsigned long rate) 201 { 202 TEE_Result res = TEE_ERROR_GENERIC; 203 unsigned long parent_rate = 0; 204 205 if (clk->parent) 206 parent_rate = clk_get_rate(clk->parent); 207 208 assert(!(clk->flags & CLK_SET_RATE_PARENT) || clk->parent); 209 if (clk->flags & CLK_SET_RATE_PARENT) { 210 res = clk_set_rate_no_lock(clk->parent, rate); 211 if (res) 212 return res; 213 rate = clk_get_rate(clk->parent); 214 } 215 216 if (clk->ops->set_rate) { 217 res = clk->ops->set_rate(clk, rate, parent_rate); 218 if (res) 219 return res; 220 } 221 222 clk_compute_rate_no_lock(clk); 223 224 return TEE_SUCCESS; 225 } 226 227 TEE_Result clk_set_rate(struct clk *clk, unsigned long rate) 228 { 229 uint32_t exceptions = 0; 230 TEE_Result res = TEE_ERROR_GENERIC; 231 232 exceptions = cpu_spin_lock_xsave(&clk_lock); 233 234 if (clk->flags & CLK_SET_RATE_GATE && clk_is_enabled_no_lock(clk)) 235 res = TEE_ERROR_BAD_STATE; 236 else 237 res = clk_set_rate_no_lock(clk, rate); 238 239 cpu_spin_unlock_xrestore(&clk_lock, exceptions); 240 241 return res; 242 } 243 244 struct clk *clk_get_parent(struct clk *clk) 245 { 246 return clk->parent; 247 } 248 249 static TEE_Result clk_get_parent_idx(struct clk *clk, struct clk *parent, 250 size_t *pidx) 251 { 252 size_t i = 0; 253 254 for (i = 0; i < clk_get_num_parents(clk); i++) { 255 if (clk_get_parent_by_index(clk, i) == parent) { 256 *pidx = i; 257 return TEE_SUCCESS; 258 } 259 } 260 EMSG("Clock %s is not a parent of clock %s", parent->name, clk->name); 261 262 return TEE_ERROR_BAD_PARAMETERS; 263 } 264 265 static TEE_Result clk_set_parent_no_lock(struct clk *clk, struct clk *parent, 266 size_t pidx) 267 { 268 TEE_Result res = TEE_ERROR_GENERIC; 269 bool was_enabled = false; 270 271 /* Requested parent is already the one set */ 272 if (clk->parent == parent) 273 return TEE_SUCCESS; 274 275 was_enabled = clk_is_enabled_no_lock(clk); 276 /* Call is needed to decrement refcount on current parent tree */ 277 if (was_enabled) 278 clk_disable_no_lock(clk); 279 280 res = clk->ops->set_parent(clk, pidx); 281 if (res) 282 goto out; 283 284 clk->parent = parent; 285 286 /* The parent changed and the rate might also have changed */ 287 clk_compute_rate_no_lock(clk); 288 289 out: 290 /* Call is needed to increment refcount on the new parent tree */ 291 if (was_enabled) { 292 res = clk_enable_no_lock(clk); 293 if (res) 294 panic("Failed to re-enable clock after setting parent"); 295 } 296 297 return res; 298 } 299 300 TEE_Result clk_set_parent(struct clk *clk, struct clk *parent) 301 { 302 size_t pidx = 0; 303 uint32_t exceptions = 0; 304 TEE_Result res = TEE_ERROR_GENERIC; 305 306 if (clk_get_parent_idx(clk, parent, &pidx) || !clk->ops->set_parent) 307 return TEE_ERROR_BAD_PARAMETERS; 308 309 exceptions = cpu_spin_lock_xsave(&clk_lock); 310 if (clk->flags & CLK_SET_PARENT_GATE && clk_is_enabled_no_lock(clk)) { 311 res = TEE_ERROR_BAD_STATE; 312 goto out; 313 } 314 315 res = clk_set_parent_no_lock(clk, parent, pidx); 316 out: 317 cpu_spin_unlock_xrestore(&clk_lock, exceptions); 318 319 return res; 320 } 321 322 TEE_Result clk_get_rates_array(struct clk *clk, size_t start_index, 323 unsigned long *rates, size_t *nb_elts) 324 { 325 if (!clk->ops->get_rates_array) 326 return TEE_ERROR_NOT_SUPPORTED; 327 328 return clk->ops->get_rates_array(clk, start_index, rates, nb_elts); 329 } 330 331 TEE_Result clk_get_duty_cycle(struct clk *clk, 332 struct clk_duty_cycle *duty_cycle) 333 { 334 if (clk->ops->get_duty_cycle) 335 return clk->ops->get_duty_cycle(clk, duty_cycle); 336 337 if (clk->parent && (clk->flags & CLK_DUTY_CYCLE_PARENT)) 338 return clk_get_duty_cycle(clk->parent, duty_cycle); 339 340 /* Default set 50% duty cycle */ 341 duty_cycle->num = 1; 342 duty_cycle->den = 2; 343 344 return TEE_SUCCESS; 345 } 346 347 /* Return updated message buffer position of NULL on failure */ 348 static __printf(3, 4) char *add_msg(char *cur, char *end, const char *fmt, ...) 349 { 350 va_list ap = { }; 351 int max_len = end - cur; 352 int ret = 0; 353 354 va_start(ap, fmt); 355 ret = vsnprintf(cur, max_len, fmt, ap); 356 va_end(ap); 357 358 if (ret < 0 || ret >= max_len) 359 return NULL; 360 361 return cur + ret; 362 } 363 364 static struct clk *find_next_clk(struct clk *parent __maybe_unused, 365 struct clk *sibling __maybe_unused) 366 { 367 struct clk *clk = NULL; 368 369 #ifdef CFG_DRIVERS_CLK_PRINT_TREE 370 if (sibling) 371 clk = SLIST_NEXT(sibling, link); 372 else 373 clk = SLIST_FIRST(&clock_list); 374 375 while (clk && clk->parent != parent) 376 clk = SLIST_NEXT(clk, link); 377 #endif 378 379 return clk; 380 } 381 382 static bool clk_is_parent_last_child(struct clk *clk) 383 { 384 return !find_next_clk(clk->parent, clk); 385 } 386 387 static bool indent_last_node_already_found(struct clk *node_clk, 388 int node_indent, int cur_indent) 389 { 390 struct clk *clk = node_clk; 391 int n = 0; 392 393 /* Find parent clock at level @node_indent - @cur_indent - 1 */ 394 for (n = 0; n < node_indent - cur_indent - 1; n++) 395 clk = clk->parent; 396 397 return clk_is_parent_last_child(clk); 398 } 399 400 static void __maybe_unused print_clk(struct clk *clk, int indent) 401 { 402 static const char * const rate_unit[] = { "Hz", "kHz", "MHz", "GHz" }; 403 int max_unit = ARRAY_SIZE(rate_unit); 404 unsigned long rate = 0; 405 char msg_buf[128] = { }; 406 char *msg_end = msg_buf + sizeof(msg_buf); 407 char *msg = msg_buf; 408 int n = 0; 409 410 /* 411 * Currently prints the clock state based on the clock refcount. 412 * A future change could print the hardware clock state when 413 * related clock driver provides a struct clk_ops::is_enabled handler 414 */ 415 416 if (indent) { 417 /* Indent for root clock level */ 418 msg = add_msg(msg, msg_end, " "); 419 if (!msg) 420 goto out; 421 422 /* Indent for root parent to clock parent levels */ 423 for (n = 0; n < indent - 1; n++) { 424 if (indent_last_node_already_found(clk, indent, n)) 425 msg = add_msg(msg, msg_end, " "); 426 else 427 msg = add_msg(msg, msg_end, "| "); 428 429 if (!msg) 430 goto out; 431 } 432 433 /* Clock indentation */ 434 if (clk_is_parent_last_child(clk)) 435 msg = add_msg(msg, msg_end, "`-- "); 436 else 437 msg = add_msg(msg, msg_end, "|-- "); 438 } else { 439 /* Root clock indentation */ 440 msg = add_msg(msg, msg_end, "o- "); 441 } 442 if (!msg) 443 goto out; 444 445 rate = clk_get_rate(clk); 446 for (n = 1; rate && !(rate % 1000) && n < max_unit; n++) 447 rate /= 1000; 448 449 msg = add_msg(msg, msg_end, "%s \t(%3s / refcnt %u / %ld %s)", 450 clk_get_name(clk), 451 refcount_val(&clk->enabled_count) ? "on " : "off", 452 refcount_val(&clk->enabled_count), 453 rate, rate_unit[n - 1]); 454 if (!msg) 455 goto out; 456 457 out: 458 if (!msg) 459 snprintf(msg_end - 4, 4, "..."); 460 461 DMSG("%s", msg_buf); 462 } 463 464 static void print_tree(void) 465 { 466 struct clk *clk = NULL; 467 struct clk *parent = NULL; 468 struct clk *next = NULL; 469 int indent = -1; 470 471 #ifdef CFG_DRIVERS_CLK_PRINT_TREE 472 if (SLIST_EMPTY(&clock_list)) { 473 DMSG("-- No registered clock"); 474 return; 475 } 476 #endif 477 478 while (true) { 479 next = find_next_clk(parent, clk); 480 if (next) { 481 print_clk(next, indent + 1); 482 /* Enter the subtree of the next clock */ 483 parent = next; 484 indent++; 485 clk = NULL; 486 } else { 487 /* 488 * We've processed all children at this level. 489 * If parent is NULL we're at the top and are done. 490 */ 491 if (!parent) 492 break; 493 /* 494 * Move up one level to resume with the next 495 * child clock of the parent. 496 */ 497 clk = parent; 498 parent = clk->parent; 499 indent--; 500 } 501 } 502 } 503 504 void clk_print_tree(void) 505 { 506 if (IS_ENABLED(CFG_DRIVERS_CLK_PRINT_TREE) && 507 TRACE_LEVEL >= TRACE_DEBUG) { 508 DMSG("Clock tree summary (informative):"); 509 print_tree(); 510 } 511 } 512