drivers: crypto: se05x: Add SCP03 keys for SE052F2

Add SCP03 default keys for SE052F2 to support OEFID 0xB501

Variant Identifier (OEF ID): B501
12NC : 9354 551 73118
Type Numb

drivers: crypto: se05x: Add SCP03 keys for SE052F2

Add SCP03 default keys for SE052F2 to support OEFID 0xB501

Variant Identifier (OEF ID): B501
12NC : 9354 551 73118
Type Number : SE052F2HN2/Z019H
Orderable Part Number : SE052F2HN2/Z019HJ

Signed-off-by: Chandni Sabharwal <chandni.sabharwal@gallagher.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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drivers: pm: sam: add code for sama7g5 LPM (Low-power Mode) pad

Set LPM pad high/low through SHDW_CR register.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklan

drivers: pm: sam: add code for sama7g5 LPM (Low-power Mode) pad

Set LPM pad high/low through SHDW_CR register.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add code for save/restore sama7g5 MCK1..4 settings

Add 2 macros for save and restore sama7g5 MCK1..4 settings.
Save MCK1..4 settings before entering the low-power modes and restore

drivers: pm: sam: add code for save/restore sama7g5 MCK1..4 settings

Add 2 macros for save and restore sama7g5 MCK1..4 settings.
Save MCK1..4 settings before entering the low-power modes and restore
the settings after exiting the low-power modes.
During the low-power mode MCK1..4 use CSS=MAINCK and DIV=1.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add support for checking sama7g5 MCK1..4 ready

sama5d2 has only MCK0 clock.
sama7g5 has MCK0,1,..., MCK4 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wi

drivers: pm: sam: add support for checking sama7g5 MCK1..4 ready

sama5d2 has only MCK0 clock.
sama7g5 has MCK0,1,..., MCK4 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: update PLLA enable/disable macros for sama7g5

Update macro "at91_plla_disable" and "at91_plla_enable" for sama7g5 PLLA.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by:

drivers: pm: sam: update PLLA enable/disable macros for sama7g5

Update macro "at91_plla_disable" and "at91_plla_enable" for sama7g5 PLLA.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: firewall: add firewall framework

Add a generic firewall controller framework. The goal of this framework
is to offer access control and configuration APIs, that are implemented
in the firewall

core: firewall: add firewall framework

Add a generic firewall controller framework. The goal of this framework
is to offer access control and configuration APIs, that are implemented
in the firewall controllers drivers, to the firewall consumers. This
framework requires an embedded device tree.

A firewall controller is an access controller [1]. It should register
itself as a provider to the framework. Firewall controllers have the
possibility to populate their bus according to defined firewall accesses
defined in the "access-controllers" property in each of the device's
node.

Any device that consumes one or more firewall should refer it/them in
their "access-controllers" property. Arguments can be passed along with
the phandle of the firewall controller(s).

Link: https://patchwork.kernel.org/project/linux-media/patch/20240105130404.301172-2-gatien.chevallier@foss.st.com/ [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add definition for sama7g5 PMC_CPU_CKR register

The offset of "PMC CPU Clock Register" for sama7g5 is different from
the one for sama5d2.

Signed-off-by: Tony Han <tony.han@microc

drivers: clk: sam: add definition for sama7g5 PMC_CPU_CKR register

The offset of "PMC CPU Clock Register" for sama7g5 is different from
the one for sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: update the count of PCK clock for sama7g5

Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks
and for sama5d2 there're 4 PCK clocks.

Signed-off-by: Tony Han <ton

drivers: pm: sam: update the count of PCK clock for sama7g5

Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks
and for sama5d2 there're 4 PCK clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: configure the wakeup sources for sama7g5

Rename the names of functions for adding the configuration of sama7g5
wakeup sources.
Add and configure the wakeup sources for sama7g5.

Si

drivers: pm: sam: configure the wakeup sources for sama7g5

Rename the names of functions for adding the configuration of sama7g5
wakeup sources.
Add and configure the wakeup sources for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: change memory area type to coherent for mapping SRAM

Mapping with memory area type MEM_AREA_TEE_RAM would enable cacheable
attribute, it might cause abort in same cases. Here chang

drivers: pm: sam: change memory area type to coherent for mapping SRAM

Mapping with memory area type MEM_AREA_TEE_RAM would enable cacheable
attribute, it might cause abort in same cases. Here change the memory
area type to MEM_AREA_TEE_COHERENT to map SRAM with non-cacheable
attribute to avoid the aborts in the low-power process.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: enable running code for low-power out of SRAM

Configure regions with write permission with not forced to
XN (Execute-never) attribute when implementation includes
the Virtualizatio

drivers: pm: sam: enable running code for low-power out of SRAM

Configure regions with write permission with not forced to
XN (Execute-never) attribute when implementation includes
the Virtualization Extensions.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: hisilicon: Update header files location

The header files in core/drivers/crypto/hisilicon/includes
are only used by the source files in core/drivers/crypto/hisilicon,
so move the he

drivers: crypto: hisilicon: Update header files location

The header files in core/drivers/crypto/hisilicon/includes
are only used by the source files in core/drivers/crypto/hisilicon,
so move the header file from core/drivers/crypto/hisilicon/include
to core/drivers/crypto/hisilicon/.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: hisilicon:Add HASH and HMAC algorithm

Add HASH and HMAC algorithm by SEC, and support SHA1,
SHA224, SHA256, SHA384, SHA512, MD5, SM3, and HMAC
algorithms based on these algorithms.

drivers: crypto: hisilicon:Add HASH and HMAC algorithm

Add HASH and HMAC algorithm by SEC, and support SHA1,
SHA224, SHA256, SHA384, SHA512, MD5, SM3, and HMAC
algorithms based on these algorithms.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: remove assertions on device handlers

Remove assertions added by the commit referred below. They are useless
since the handlers are registered only if the related device (stm32_cryp

drivers: crypto: remove assertions on device handlers

Remove assertions added by the commit referred below. They are useless
since the handlers are registered only if the related device (stm32_cryp
or stm32_saes) has its driver successfully probed. These assertion also
prevent enabling both CFG_STM32_SAES and CFG_STM32_CRYP for a platform
which is a valid configuration for when we rely on the DT to state
which of both is enabled.

Fixes: 03de2c7bb316 ("drivers: crypto: stm32_saes: fallback to software on 192bit AES keys")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>

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drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driv

drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driver that uses FFA interface to print trace logs.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: regulator: split regulator_supported_voltages() assertions

Split assertions in regulator_supported_voltages() to ease debugging,
providing a better indication of which condition is not fulf

drivers: regulator: split regulator_supported_voltages() assertions

Split assertions in regulator_supported_voltages() to ease debugging,
providing a better indication of which condition is not fulfilled.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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drivers: regulator: fix error case in regulator_supported_voltages()

Fix case when .supported_voltages() handler is supported. If successful
it shall assert voltage description data. If it returns
T

drivers: regulator: fix error case in regulator_supported_voltages()

Fix case when .supported_voltages() handler is supported. If successful
it shall assert voltage description data. If it returns
TEE_ERROR_NOT_SUPPORTED, it shall use the pre-filled fallback description.

Fixes: af5b9881111c ("drivers: regulator: supported voltage consider levels bounds")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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drivers: pm: sam: map SFRBU with DT_MAP_SECURE attribute for sama7g5

As sama7g5's SFRBU is always secured map it as secured and do not
need to configure the security through the matrix.

Signed-off-

drivers: pm: sam: map SFRBU with DT_MAP_SECURE attribute for sama7g5

As sama7g5's SFRBU is always secured map it as secured and do not
need to configure the security through the matrix.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: rename pm_init functions for later sama7g5 support

PM support for sama7g5 will reuse some existing functions.
Rename sama5d2_pm_init() to sam_pm_init().
Rename sama5d2_pm_init_all(

drivers: pm: sam: rename pm_init functions for later sama7g5 support

PM support for sama7g5 will reuse some existing functions.
Rename sama5d2_pm_init() to sam_pm_init().
Rename sama5d2_pm_init_all() to sam_pm_init_all().

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: atmel_shdwc: enable RTT (Real-time Timer) Wake-up

For sama7g5 the Wake-up can be caused by RTT.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@li

drivers: atmel_shdwc: enable RTT (Real-time Timer) Wake-up

For sama7g5 the Wake-up can be caused by RTT.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: atmel_shdwc: update to call the initialize for PM for sama7g5

For sama7g5 case do not return before calling the initialize function
for PM.

Signed-off-by: Tony Han <tony.han@microchip.com>

drivers: atmel_shdwc: update to call the initialize for PM for sama7g5

For sama7g5 case do not return before calling the initialize function
for PM.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers:implement HiSilicon Security Engine(SEC) module.

HiSilicon SEC is used in security applications such as
authentication and data encryption and decryption. This
module implement the hardware

drivers:implement HiSilicon Security Engine(SEC) module.

HiSilicon SEC is used in security applications such as
authentication and data encryption and decryption. This
module implement the hardware initialization of the SEC.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: hisilicon: add DH algorithm

add operation of DH algorithm, including alloc_keypair,
gen_keypair and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Etienne Car

drivers: crypto: hisilicon: add DH algorithm

add operation of DH algorithm, including alloc_keypair,
gen_keypair and shared_secret

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: Add RISC-V Zkr hardware random number generator support

The RISC-V Zkr entropy source extension introduces a physical
entropy source compliant with NIST SP 800-90B or BSI AIS-31
standards v

drivers: Add RISC-V Zkr hardware random number generator support

The RISC-V Zkr entropy source extension introduces a physical
entropy source compliant with NIST SP 800-90B or BSI AIS-31
standards via the seed CSR.

Note that this driver cannot be used unless access is explicitly
granted by M-mode, e.g. OpenSBI have to set mseccfg.SSEED for
OP-TEE OS.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: add IPCC driver and its RIF support

This driver implements RIF configuration for IPCC, which is a RIF
aware IP. It means that the IPCC driver is in charge of configuring its
own RIF restric

drivers: add IPCC driver and its RIF support

This driver implements RIF configuration for IPCC, which is a RIF
aware IP. It means that the IPCC driver is in charge of configuring its
own RIF restrictions and that the IPCC has dedicated RIF configuration
registers.

RIF configuration data is part of the ipcc_pdata structure.

CID filtering is applied to the entirety of the channels of a processor.
When CID filtering is enabled for a processor, it enables the filtering and
the IPCC interrupt routing for all of its IPCC channels.

However, security and privilege configuration granularity go as far as
configuration for each IPCC channel.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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