1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 2/* 3 * This file was imported from Linux arch/arm/mach-at91/pm_suspend.S and 4 * relicensed with dual GPL-2.0/BSD-2-Clause with Microchip agreement. 5 * 6 * Copyright (c) 2021, Microchip 7 */ 8 9#include <arm.h> 10#include <arm32_macros.S> 11#include <asm.S> 12#include <at91_pmc.h> 13#include <drivers/sam/at91_ddr.h> 14#include <generated/pm-defines.h> 15 16#include "at91_pm.h" 17 18#define SRAMC_SELF_FRESH_ACTIVE 0x01 19#define SRAMC_SELF_FRESH_EXIT 0x00 20 21pmc .req r0 22tmp1 .req r4 23tmp2 .req r5 24tmp3 .req r6 25 26/* 27 * Wait until master clock is ready (after switching master clock source) 28 */ 29.macro wait_mckrdy 301: ldr tmp1, [pmc, #AT91_PMC_SR] 31 tst tmp1, #AT91_PMC_MCKRDY 32 beq 1b 33.endm 34 35/* 36 * Wait until master oscillator has stabilized. 37 */ 38.macro wait_moscrdy 391: ldr tmp1, [pmc, #AT91_PMC_SR] 40 tst tmp1, #AT91_PMC_MOSCS 41 beq 1b 42.endm 43 44/* 45 * Wait for main oscillator selection is done 46 */ 47.macro wait_moscsels 481: ldr tmp1, [pmc, #AT91_PMC_SR] 49 tst tmp1, #AT91_PMC_MOSCSELS 50 beq 1b 51.endm 52 53/* 54 * Put the processor to enter the idle state 55 */ 56.macro at91_cpu_idle 57 58 mov tmp1, #AT91_PMC_PCK 59 str tmp1, [pmc, #AT91_PMC_SCDR] 60 61 dsb 62 63 wfi @ Wait For Interrupt 64 65.endm 66 67.section .text.psci.suspend 68 69.arm 70 71 72#define SUSPEND_FUNC(__name) \ 73__name: 74 75#define SUSPEND_END_FUNC(__name) \ 76 .size __name, .-__name 77 78.macro check_fit_in_sram since 79 .if (. - \since) > 0x10000 80 .error "Suspend assembly code exceeds dedicated SRAM size" 81 .endif 82.endm 83 84/* 85 * void at91_suspend_sram_fn(struct at91_pm_data*) 86 * @input param: 87 * @r0: base address of struct at91_pm_data 88 */ 89.align 3 90.global at91_pm_suspend_in_sram 91SUSPEND_FUNC(at91_pm_suspend_in_sram) 92 /* Save registers on stack */ 93 stmfd sp!, {r4 - r12, lr} 94 95 /* Drain write buffer */ 96 mov tmp1, #0 97 mcr p15, 0, tmp1, c7, c10, 4 98 99 ldr tmp1, [r0, #PM_DATA_PMC] 100 str tmp1, .pmc_base 101 ldr tmp1, [r0, #PM_DATA_RAMC0] 102 str tmp1, .sramc_base 103 ldr tmp1, [r0, #PM_DATA_MODE] 104 str tmp1, .pm_mode 105 /* Both ldrne below are here to preload their address in the TLB */ 106 ldr tmp1, [r0, #PM_DATA_SHDWC] 107 str tmp1, .shdwc 108 cmp tmp1, #0 109 ldrne tmp2, [tmp1, #0] 110 ldr tmp1, [r0, #PM_DATA_SFRBU] 111 str tmp1, .sfrbu 112 cmp tmp1, #0 113 ldrne tmp2, [tmp1, #0x10] 114 115 /* Active the self-refresh mode */ 116 mov r0, #SRAMC_SELF_FRESH_ACTIVE 117 bl at91_sramc_self_refresh 118 119 ldr r0, .pm_mode 120 cmp r0, #AT91_PM_STANDBY 121 beq standby 122 cmp r0, #AT91_PM_BACKUP 123 beq backup_mode 124 125 bl at91_ulp_mode 126 b exit_suspend 127 128standby: 129 /* Wait for interrupt */ 130 ldr pmc, .pmc_base 131 at91_cpu_idle 132 b exit_suspend 133 134backup_mode: 135 bl at91_backup_mode 136 b exit_suspend 137 138exit_suspend: 139 /* Exit the self-refresh mode */ 140 mov r0, #SRAMC_SELF_FRESH_EXIT 141 bl at91_sramc_self_refresh 142 143 /* Restore registers, and return */ 144 ldmfd sp!, {r4 - r12, pc} 145SUSPEND_END_FUNC(at91_pm_suspend_in_sram) 146 147SUSPEND_FUNC(at91_backup_mode) 148 /* Switch the master clock source to slow clock. */ 149 ldr pmc, .pmc_base 150 ldr tmp1, [pmc, #AT91_PMC_MCKR] 151 bic tmp1, tmp1, #AT91_PMC_CSS 152 str tmp1, [pmc, #AT91_PMC_MCKR] 153 154 wait_mckrdy 155 156 /*BUMEN*/ 157 ldr r0, .sfrbu 158 mov tmp1, #0x1 159 str tmp1, [r0, #0x10] 160 161 /* Shutdown */ 162 ldr r0, .shdwc 163 mov tmp1, #0xA5000000 164 add tmp1, tmp1, #0x1 165 str tmp1, [r0, #0] 166SUSPEND_END_FUNC(at91_backup_mode) 167 168.macro at91_pm_ulp0_mode 169 ldr pmc, .pmc_base 170 ldr tmp2, .pm_mode 171 172 /* Check if ULP0 fast variant has been requested. */ 173 cmp tmp2, #AT91_PM_ULP0_FAST 174 bne 0f 175 176 /* Set highest prescaler for power saving */ 177 ldr tmp1, [pmc, #AT91_PMC_MCKR] 178 bic tmp1, tmp1, #AT91_PMC_PRES 179 orr tmp1, tmp1, #AT91_PMC_PRES_64 180 str tmp1, [pmc, #AT91_PMC_MCKR] 181 wait_mckrdy 182 b 1f 183 1840: 185 /* Turn off the crystal oscillator */ 186 ldr tmp1, [pmc, #AT91_CKGR_MOR] 187 bic tmp1, tmp1, #AT91_PMC_MOSCEN 188 orr tmp1, tmp1, #AT91_PMC_KEY 189 str tmp1, [pmc, #AT91_CKGR_MOR] 190 191 /* Save RC oscillator state */ 192 ldr tmp1, [pmc, #AT91_PMC_SR] 193 str tmp1, .saved_osc_status 194 tst tmp1, #AT91_PMC_MOSCRCS 195 bne 1f 196 197 /* Turn off RC oscillator */ 198 ldr tmp1, [pmc, #AT91_CKGR_MOR] 199 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 200 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 201 orr tmp1, tmp1, #AT91_PMC_KEY 202 str tmp1, [pmc, #AT91_CKGR_MOR] 203 204 /* Wait main RC disabled done */ 2052: ldr tmp1, [pmc, #AT91_PMC_SR] 206 tst tmp1, #AT91_PMC_MOSCRCS 207 bne 2b 208 209 /* Wait for interrupt */ 2101: at91_cpu_idle 211 212 /* Check if ULP0 fast variant has been requested. */ 213 cmp tmp2, #AT91_PM_ULP0_FAST 214 bne 5f 215 216 /* Set lowest prescaler for fast resume. */ 217 ldr tmp1, [pmc, #AT91_PMC_MCKR] 218 bic tmp1, tmp1, #AT91_PMC_PRES 219 str tmp1, [pmc, #AT91_PMC_MCKR] 220 wait_mckrdy 221 b 6f 222 2235: /* Restore RC oscillator state */ 224 ldr tmp1, .saved_osc_status 225 tst tmp1, #AT91_PMC_MOSCRCS 226 beq 4f 227 228 /* Turn on RC oscillator */ 229 ldr tmp1, [pmc, #AT91_CKGR_MOR] 230 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 231 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 232 orr tmp1, tmp1, #AT91_PMC_KEY 233 str tmp1, [pmc, #AT91_CKGR_MOR] 234 235 /* Wait main RC stabilization */ 2363: ldr tmp1, [pmc, #AT91_PMC_SR] 237 tst tmp1, #AT91_PMC_MOSCRCS 238 beq 3b 239 240 /* Turn on the crystal oscillator */ 2414: ldr tmp1, [pmc, #AT91_CKGR_MOR] 242 orr tmp1, tmp1, #AT91_PMC_MOSCEN 243 orr tmp1, tmp1, #AT91_PMC_KEY 244 str tmp1, [pmc, #AT91_CKGR_MOR] 245 246 wait_moscrdy 2476: 248.endm 249 250/** 251 * Note: This procedure only applies on the platform which uses 252 * the external crystal oscillator as a main clock source. 253 */ 254.macro at91_pm_ulp1_mode 255 ldr pmc, .pmc_base 256 257 /* Save RC oscillator state and check if it is enabled. */ 258 ldr tmp1, [pmc, #AT91_PMC_SR] 259 str tmp1, .saved_osc_status 260 tst tmp1, #AT91_PMC_MOSCRCS 261 bne 2f 262 263 /* Enable RC oscillator */ 264 ldr tmp1, [pmc, #AT91_CKGR_MOR] 265 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN 266 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 267 orr tmp1, tmp1, #AT91_PMC_KEY 268 str tmp1, [pmc, #AT91_CKGR_MOR] 269 270 /* Wait main RC stabilization */ 2711: ldr tmp1, [pmc, #AT91_PMC_SR] 272 tst tmp1, #AT91_PMC_MOSCRCS 273 beq 1b 274 275 /* Switch the main clock source to 12-MHz RC oscillator */ 2762: ldr tmp1, [pmc, #AT91_CKGR_MOR] 277 bic tmp1, tmp1, #AT91_PMC_MOSCSEL 278 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 279 orr tmp1, tmp1, #AT91_PMC_KEY 280 str tmp1, [pmc, #AT91_CKGR_MOR] 281 282 wait_moscsels 283 284 /* Disable the crystal oscillator */ 285 ldr tmp1, [pmc, #AT91_CKGR_MOR] 286 bic tmp1, tmp1, #AT91_PMC_MOSCEN 287 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 288 orr tmp1, tmp1, #AT91_PMC_KEY 289 str tmp1, [pmc, #AT91_CKGR_MOR] 290 291 /* Switch the master clock source to main clock */ 292 ldr tmp1, [pmc, #AT91_PMC_MCKR] 293 bic tmp1, tmp1, #AT91_PMC_CSS 294 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 295 str tmp1, [pmc, #AT91_PMC_MCKR] 296 297 wait_mckrdy 298 299 /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ 300 ldr tmp1, [pmc, #AT91_CKGR_MOR] 301 orr tmp1, tmp1, #AT91_PMC_WAITMODE 302 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 303 orr tmp1, tmp1, #AT91_PMC_KEY 304 str tmp1, [pmc, #AT91_CKGR_MOR] 305 306 /* Quirk for SAM9X60's PMC */ 307 nop 308 nop 309 310 wait_mckrdy 311 312 /* Enable the crystal oscillator */ 313 ldr tmp1, [pmc, #AT91_CKGR_MOR] 314 orr tmp1, tmp1, #AT91_PMC_MOSCEN 315 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 316 orr tmp1, tmp1, #AT91_PMC_KEY 317 str tmp1, [pmc, #AT91_CKGR_MOR] 318 319 wait_moscrdy 320 321 /* Switch the master clock source to slow clock */ 322 ldr tmp1, [pmc, #AT91_PMC_MCKR] 323 bic tmp1, tmp1, #AT91_PMC_CSS 324 str tmp1, [pmc, #AT91_PMC_MCKR] 325 326 wait_mckrdy 327 328 /* Switch main clock source to crystal oscillator */ 329 ldr tmp1, [pmc, #AT91_CKGR_MOR] 330 orr tmp1, tmp1, #AT91_PMC_MOSCSEL 331 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 332 orr tmp1, tmp1, #AT91_PMC_KEY 333 str tmp1, [pmc, #AT91_CKGR_MOR] 334 335 wait_moscsels 336 337 /* Switch the master clock source to main clock */ 338 ldr tmp1, [pmc, #AT91_PMC_MCKR] 339 bic tmp1, tmp1, #AT91_PMC_CSS 340 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 341 str tmp1, [pmc, #AT91_PMC_MCKR] 342 343 wait_mckrdy 344 345 /* Restore RC oscillator state */ 346 ldr tmp1, .saved_osc_status 347 tst tmp1, #AT91_PMC_MOSCRCS 348 bne 3f 349 350 /* Disable RC oscillator */ 351 ldr tmp1, [pmc, #AT91_CKGR_MOR] 352 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN 353 bic tmp1, tmp1, #AT91_PMC_KEY_MASK 354 orr tmp1, tmp1, #AT91_PMC_KEY 355 str tmp1, [pmc, #AT91_CKGR_MOR] 356 357 /* Wait RC oscillator disable done */ 3584: ldr tmp1, [pmc, #AT91_PMC_SR] 359 tst tmp1, #AT91_PMC_MOSCRCS 360 bne 4b 361 3623: 363.endm 364 365/* 366 * Save PLLA setting and disable it 367 * 368 * Side effects: overwrites tmp1, tmp2 369 */ 370.macro at91_plla_disable 371#ifdef CFG_SAMA7G5 372 /* Save PLLA settings */ 373 ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] 374 bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID 375 str tmp2, [pmc, #AT91_PMC_PLL_UPDT] 376 377 /* save div */ 378 mov tmp1, #0 379 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] 380 bic tmp2, tmp2, #0xffffff00 381 orr tmp1, tmp1, tmp2 382 383 /* save mul */ 384 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1] 385 bic tmp2, tmp2, #0xffffff 386 orr tmp1, tmp1, tmp2 387 str tmp1, .saved_pllar 388 389 /* step 2 */ 390 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 391 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 392 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 393 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 394 395 /* step 3 */ 396 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 397 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 398 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 399 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 400 401 /* step 4 */ 402 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 403 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 404 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 405 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 406 407 /* step 5 */ 408 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 409 bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 410 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 411 412 /* step 6 */ 413 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 414 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 415 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 416 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 417#else 418 /* Save PLLA setting and disable it */ 419 ldr tmp1, [pmc, #AT91_CKGR_PLLAR] 420 str tmp1, .saved_pllar 421 422 /* Disable PLLA. */ 423 mov tmp1, #AT91_PMC_PLLCOUNT 424 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ 425 str tmp1, [pmc, #AT91_CKGR_PLLAR] 426#endif 4272: 428.endm 429 430/* 431 * Enable PLLA with the saved setting 432 * 433 * Side effects: overwrites tmp1, tmp2 434 */ 435.macro at91_plla_enable 436#ifdef CFG_SAMA7G5 437 /* step 1 */ 438 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 439 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 440 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 441 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 442 443 /* step 2 */ 444 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA 445 str tmp1, [pmc, #AT91_PMC_PLL_ACR] 446 447 /* step 3 */ 448 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 449 ldr tmp2, .saved_pllar 450 bic tmp2, tmp2, #0xffffff 451 orr tmp1, tmp1, tmp2 452 str tmp1, [pmc, #AT91_PMC_PLL_CTRL1] 453 454 /* step 4 */ 455 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 456 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 457 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 458 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 459 460 /* step 5 */ 461 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 462 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK 463 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL 464 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK 465 bic tmp1, tmp1, #0xff 466 ldr tmp2, .saved_pllar 467 bic tmp2, tmp2, #0xffffff00 468 orr tmp1, tmp1, tmp2 469 str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] 470 471 /* step 6 */ 472 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] 473 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE 474 bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID 475 str tmp1, [pmc, #AT91_PMC_PLL_UPDT] 476 477 /* step 7 */ 4783: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0] 479 tst tmp1, #0x1 480 beq 3b 481#else 482 ldr tmp2, .saved_pllar 483 484 /* Restore PLLA setting */ 485 str tmp2, [pmc, #AT91_CKGR_PLLAR] 486 487 /* Enable PLLA. */ 488 tst tmp2, #(AT91_PMC_MUL & 0xff0000) 489 bne 1f 490 tst tmp2, #(AT91_PMC_MUL & ~0xff0000) 491 beq 2f 492 4931: ldr tmp1, [pmc, #AT91_PMC_SR] 494 tst tmp1, #AT91_PMC_LOCKA 495 beq 1b 4962: 497#endif 498.endm 499 500SUSPEND_FUNC(at91_ulp_mode) 501 ldr pmc, .pmc_base 502 ldr tmp3, .pm_mode 503 504 /* Save Master clock setting */ 505 ldr tmp1, [pmc, #AT91_PMC_MCKR] 506 str tmp1, .saved_mckr 507 508 /* 509 * Set master clock source to: 510 * - MAINCK if using ULP0 fast variant 511 * - slow clock, otherwise 512 */ 513 bic tmp1, tmp1, #AT91_PMC_CSS 514 cmp tmp3, #AT91_PM_ULP0_FAST 515 bne save_mck 516 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN 517save_mck: 518 str tmp1, [pmc, #AT91_PMC_MCKR] 519 520 wait_mckrdy 521 522 at91_plla_disable 523 524 cmp tmp3, #AT91_PM_ULP1 525 beq ulp1_mode 526 527 at91_pm_ulp0_mode 528 b ulp_exit 529 530ulp1_mode: 531 at91_pm_ulp1_mode 532 b ulp_exit 533 534ulp_exit: 535 ldr pmc, .pmc_base 536 537 at91_plla_enable 538 539 /* 540 * Restore master clock setting 541 */ 542 ldr tmp2, .saved_mckr 543 str tmp2, [pmc, #AT91_PMC_MCKR] 544 545 wait_mckrdy 546 547 mov pc, lr 548SUSPEND_END_FUNC(at91_ulp_mode) 549 550/* 551 * void at91_sramc_self_refresh(unsigned int is_active) 552 * 553 * @input param: 554 * @r0: 1 - active self-refresh mode 555 * 0 - exit self-refresh mode 556 * register usage: 557 * @r2: base address of the sram controller 558 */ 559 560SUSPEND_FUNC(at91_sramc_self_refresh) 561 ldr r2, .sramc_base 562 563 /* 564 * DDR Memory controller 565 */ 566 tst r0, #SRAMC_SELF_FRESH_ACTIVE 567 beq ddrc_exit_sf 568 569 /* LPDDR1 --> force DDR2 mode during self-refresh */ 570 ldr r3, [r2, #AT91_DDRSDRC_MDR] 571 str r3, .saved_sam9_mdr 572 bic r3, r3, #~AT91_DDRSDRC_MD 573 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR 574 ldreq r3, [r2, #AT91_DDRSDRC_MDR] 575 biceq r3, r3, #AT91_DDRSDRC_MD 576 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 577 streq r3, [r2, #AT91_DDRSDRC_MDR] 578 579 /* Active DDRC self-refresh mode */ 580 ldr r3, [r2, #AT91_DDRSDRC_LPR] 581 str r3, .saved_sam9_lpr 582 bic r3, r3, #AT91_DDRSDRC_LPCB 583 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 584 str r3, [r2, #AT91_DDRSDRC_LPR] 585 586 b exit_sramc_sf 587 588ddrc_exit_sf: 589 /* Restore MDR in case of LPDDR1 */ 590 ldr r3, .saved_sam9_mdr 591 str r3, [r2, #AT91_DDRSDRC_MDR] 592 /* Restore LPR on AT91 with DDRAM */ 593 ldr r3, .saved_sam9_lpr 594 str r3, [r2, #AT91_DDRSDRC_LPR] 595 596exit_sramc_sf: 597 mov pc, lr 598SUSPEND_END_FUNC(at91_sramc_self_refresh) 599 600.pmc_base: 601 .word 0 602.sramc_base: 603 .word 0 604.shdwc: 605 .word 0 606.sfrbu: 607 .word 0 608.pm_mode: 609 .word 0 610.saved_mckr: 611 .word 0 612.saved_pllar: 613 .word 0 614.saved_sam9_lpr: 615 .word 0 616.saved_sam9_mdr: 617 .word 0 618.saved_osc_status: 619 .word 0 620 621.global at91_pm_suspend_in_sram_sz 622at91_pm_suspend_in_sram_sz: 623 .word .-at91_pm_suspend_in_sram 624 625check_fit_in_sram at91_pm_suspend_in_sram 626