driver: crypto: hisilicon: add ECC sign and verify

add ECC sign and verify

Signed-off-by: yuzexi <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: ele: enable support for i.MX91

Enable ELE driver support for i.MX91.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: imx_mu: enable support for i.MX91

Enable MU driver support for i.MX91

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

drivers: nvmem: nvmem-huk: fix cell size and memory allocation issues

No longer free the HUK cell after at the end of the
"tee_otp_get_hw_unique_key" execution, because for the regression
test 4013,

drivers: nvmem: nvmem-huk: fix cell size and memory allocation issues

No longer free the HUK cell after at the end of the
"tee_otp_get_hw_unique_key" execution, because for the regression
test 4013, the "tee_otp_get_hw_unique_key" callback isn't
re-called then an invalid huk_cell pointer is used, leading the
following issue:

E/TC:0 0 Core data-abort at address 0x0 (translation fault)
E/TC:0 0 fsr 0x00000005 ttbr0 0x20087859 ttbr1 0x20080059 cidr 0x2
E/TC:0 0 cpu #0 cpsr 0x60000133
E/TC:0 0 r0 0x2007d8e8 r4 0x2007d8e8 r8 0x00102010 r12 0xfffc2a40
E/TC:0 0 r1 0x20089528 r5 0x2008954c r9 0x00000010 sp 0x20089508
E/TC:0 0 r2 0x20059164 r6 0x20060188 r10 0x00000020 lr 0x2000bcb3
E/TC:0 0 r3 0x00000000 r7 0x2008954c r11 0x20089684 pc 0x2000baa2
E/TC:0 0 TEE load address @ 0x20000000
E/TC:0 0 Call stack:
E/TC:0 0 0x2000baa2 nvmem_cell_malloc_and_read at core/drivers/nvmem/nvmem.c:62
E/TC:0 0 0x2000bcb3 tee_otp_get_hw_unique_key at core/drivers/nvmem/nvmem_huk.c:23
E/TC:0 0 0x20010e9f __huk_subkey_derive at core/kernel/huk_subkey.c:78
E/TC:0 0 0x200178c9 system_derive_ta_unique_key at core/pta/system.c:122
E/TC:0 0 0x2001382b pseudo_ta_enter_invoke_cmd at core/kernel/pseudo_ta.c:209
E/TC:0 0 0x20010d95 tee_ta_invoke_command at core/kernel/tee_ta_manager.c:765
E/TC:0 0 0x20019567 syscall_invoke_ta_command at core/tee/tee_svc.c:871
E/TC:0 0 0x20002178 scall_do_call at core/arch/arm/kernel/arch_scall_a32.S:54
E/TC:0 0 Panic 'unhandled pageable abort' at core/arch/arm/kernel/abort.c:582 <abort_handler>
E/TC:0 0 TEE load address @ 0x20000000
E/TC:0 0 Call stack:
E/TC:0 0 0x200039b1 print_kernel_stack at core/arch/arm/kernel/unwind_arm32.c:109
E/TC:0 0 0x2000ff05 __do_panic at core/kernel/panic.c:80
E/TC:0 0 0x20002f01 get_fault_type at core/arch/arm/kernel/abort.c:498
E/TC:0 0 0x2000077c thread_excp_vect at core/arch/arm/kernel/thread_a32.S:758

Moreover, the length of the HW unique key must be 16 bytes.
But the size of NVMEM cells can be larger than 16 bytes, for
example on samad5 the SFC is using 32 bytes cells. These changes
also allow the use of a NVMEM cell larger to the HW unique key
length, using the first 16 bytes of a cell.

Finally, the instance of the NVMEM cell data will be allocated once,
in the probe. Before, a new instance was allocated at each call
to tee_otp_get_hw_unique_key().

Fixes: fc7169686724 ("drivers: nvmem: add nvmem-huk driver")
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: nvmem: nvmem-die-id: fix cell length

Obviously, the cell length wasn't set during nvmem-die-id
driver probe and the subkey length was always used.

Signed-off-by: Thomas Perrot <thomas.perr

drivers: nvmem: nvmem-die-id: fix cell length

Obviously, the cell length wasn't set during nvmem-die-id
driver probe and the subkey length was always used.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: nvmem: atmel_sfc: check the length before read cell

Check requested NVMEM cells length in Atmel SFC driver to
prevent issues in case the length is greater than the fuse
size.

Signed-off-by

drivers: nvmem: atmel_sfc: check the length before read cell

Check requested NVMEM cells length in Atmel SFC driver to
prevent issues in case the length is greater than the fuse
size.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: dt_driver: fix nodes reference passed in dt_pargs

Correct the DT node references passed in struct dt_pargs. Field
phandle_node is expected to be the node offset of the provider driver

core: kernel: dt_driver: fix nodes reference passed in dt_pargs

Correct the DT node references passed in struct dt_pargs. Field
phandle_node is expected to be the node offset of the provider driver
but dt_driver_device_from_node_idx_prop_phandle() implementation passes
node offset -1, dt_driver_device_from_parent() passes the consumer
node offset and dt_driver_device_from_node_idx_prop() may pass the
phandle node offset from a previous index in the parsed DT node property.

Fix that by adding field consumer_node to reference the node offset of
the consumer device and fixing phandle_node where applicable and
update atmel_i2c and stm32_i2c drivers to get the I2C device address
from the consumer_node field instead of the phandle_node that is now
fixed.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: crypto: hisilicon: fix incorrect use of error code

Fix incorrect use of memory-related error code in hash algorithm.

Fixes: 94c8a3397ec4 ("drivers: crypto: hisilicon:Add HASH and HMAC algo

drivers: crypto: hisilicon: fix incorrect use of error code

Fix incorrect use of memory-related error code in hash algorithm.

Fixes: 94c8a3397ec4 ("drivers: crypto: hisilicon:Add HASH and HMAC algorithm")
Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: hisilicon: Add cipher algorithm

Add DES, 3DES, AES and SM4 cipher algorithm

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by

drivers: crypto: hisilicon: Add cipher algorithm

Add DES, 3DES, AES and SM4 cipher algorithm

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32: add an error trace when registering CRYP and SAES

Drvcrypt framework can only register one symmetric cipher driver.
Add an explicit error trace in function stm32_register_cip

drivers: crypto: stm32: add an error trace when registering CRYP and SAES

Drvcrypt framework can only register one symmetric cipher driver.
Add an explicit error trace in function stm32_register_cipher() when
several cipher drivers are registered.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: crypto: stm32_saes: SAES depends on RNG clock

Fixes missing dependency of SAES device on RNG clock.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Thomas Bou

drivers: crypto: stm32_saes: SAES depends on RNG clock

Fixes missing dependency of SAES device on RNG clock.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: crypto: stm32_saes: add PM to SAES driver

Add power management support to the SAES driver through suspend/resume
callbacks.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
S

drivers: crypto: stm32_saes: add PM to SAES driver

Add power management support to the SAES driver through suspend/resume
callbacks.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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driver: crypto: hisilicon: add ECC gen_keypair and ECDH

add ECC gen_keypair and ECDH

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

core: firewall: fix warning when compiling with no trace.

When compiling with CFG_TEE_CORE_LOG_LEVEL=0 this warning is raised :
core/drivers/firewall/firewall.c: In function ‘firewall_dt_probe_bus’:

core: firewall: fix warning when compiling with no trace.

When compiling with CFG_TEE_CORE_LOG_LEVEL=0 this warning is raised :
core/drivers/firewall/firewall.c: In function ‘firewall_dt_probe_bus’:
core/drivers/firewall/firewall.c:297:62: error: unused parameter ‘ctrl’ [-Werror=unused-parameter]
297 | struct firewall_controller *ctrl)

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: drivers: relicense hisi_trng.c as BSD-2-Clause

The file core/drivers/hisi_trng.c should not have been committed with a
GPL-2.0 license. Relicense it as BSD-2-Clause.

Signed-off-by: Jerome For

core: drivers: relicense hisi_trng.c as BSD-2-Clause

The file core/drivers/hisi_trng.c should not have been committed with a
GPL-2.0 license. Relicense it as BSD-2-Clause.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Closes: https://github.com/OP-TEE/optee_os/issues/6834
Acked-by: loubaihui <loubaihui1@huawei.com>
Acked-by: leisen <leisen1@huawei.com>

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drivers: stm32_rstctrl: fix unpaged resource

Fixes missing declaration of STM32MP1 reset controller compat data
as unpaged resource since it is used by stm32mp_rcc_reset_id_to_rstctrl()
function ca

drivers: stm32_rstctrl: fix unpaged resource

Fixes missing declaration of STM32MP1 reset controller compat data
as unpaged resource since it is used by stm32mp_rcc_reset_id_to_rstctrl()
function called by fastcall service psci_system_reset() that requires
to resized in the unpaged segment on STM32MP15 variant where pager
is enabled.

Fixes: 3ef177b4f153 ("drivers: stm32_rstctrl: move stm32mp1x controller in stm32mp1_rstcrl.c")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: rstctrl: add reset controller for STM32MP25 platforms

Implement the STM32MP25 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.

Signed-off-by: G

drivers: rstctrl: add reset controller for STM32MP25 platforms

Implement the STM32MP25 reset controller device by embedding it
with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rstctrl: move stm32mp1x controller in stm32mp1_rstcrl.c

This change prepares the STM32MP25 reset controller driver.
The binding for the STM32MP25 is different from that of the
STM32MP

drivers: stm32_rstctrl: move stm32mp1x controller in stm32mp1_rstcrl.c

This change prepares the STM32MP25 reset controller driver.
The binding for the STM32MP25 is different from that of the
STM32MP1x, so we will create a stm32mp25_rstcrl.c file.
This change factorizes STM32 API functions in stm32_rstcrl.c file
for probing and passing platform data.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st

clk: stm32mp25: Introduce STM32MP25 clocks platform

This driver is based on clk-stm32-core API to manage STM32 gates, dividers
and muxes.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: pass TEE_ATTR_RSA_OAEP_MGF_HASH to RSA-OAEP implementations

OP-TEE currently doesn't support using a different hash for MGF1
with RSA-OAEP. However, this is required for AOSP compatibility
(e.

core: pass TEE_ATTR_RSA_OAEP_MGF_HASH to RSA-OAEP implementations

OP-TEE currently doesn't support using a different hash for MGF1
with RSA-OAEP. However, this is required for AOSP compatibility
(e.g. in EncryptionOperationsTest.RsaOaepWithMGFDigestSuccess [1]).

Pass the MGF1 attribute to crypto implementations. Note that
only libtomcrypt supports this feature at the moment, so other
implementations will either fail or fall back to libtomcrypt when
passed a different MGF1 hash.

Link: https://android.googlesource.com/platform/hardware/interfaces/+/refs/heads/main/security/keymint/aidl/vts/functional/KeyMintTest.cpp#5552 [1]
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: clk: sam: add the implement of CPU OPP clock

Register CPU OPP clock with the following operations:
- set_rate: call the operation of its parent
- get_rates_array: return the rates got fro

drivers: clk: sam: add the implement of CPU OPP clock

Register CPU OPP clock with the following operations:
- set_rate: call the operation of its parent
- get_rates_array: return the rates got from DT.
Skip CPU OPP clock register when OPP is not supported.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: prepare for CPU OPP (Operating Performance Points) support

Initialize clock rates array by parsing the device tree.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carr

plat-sam: prepare for CPU OPP (Operating Performance Points) support

Initialize clock rates array by parsing the device tree.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: pm: sam: improve the access of variables in "at91_pm_data"

Flush the TLB before accessing variables in "at91_pm_data".
Preload the variables before using.

Signed-off-by: Tony Han <tony.han

drivers: pm: sam: improve the access of variables in "at91_pm_data"

Flush the TLB before accessing variables in "at91_pm_data".
Preload the variables before using.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode

Add the header file "sama7-ddr.h" for sama7g5 DRAM controller.
Add 2 macros for enable and disable sama7g5 DRAM self-refr

drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode

Add the header file "sama7-ddr.h" for sama7g5 DRAM controller.
Add 2 macros for enable and disable sama7g5 DRAM self-refresh mode.
Enable self-refresh mode before entering the low-power modes and
disable it after exiting the low-power modes.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add code for the phy of sama7g5 dram controller

Add and initilate the variable for the start address of sama7g5
dram controller phy.

Signed-off-by: Tony Han <tony.han@microchip.co

drivers: pm: sam: add code for the phy of sama7g5 dram controller

Add and initilate the variable for the start address of sama7g5
dram controller phy.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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