| 24bb7516 | 16-Nov-2017 |
wangwen <wangwen@marvell.com> |
plat-marvell: Add initial support for ARMADA3700
Only test 64bit mode with default configuration
1. Build command
make PLATFORM=marvell-armada3700
2. Pass xtest
Signed-off-by: wangwen <wangwen
plat-marvell: Add initial support for ARMADA3700
Only test 64bit mode with default configuration
1. Build command
make PLATFORM=marvell-armada3700
2. Pass xtest
Signed-off-by: wangwen <wangwen@marvell.comi>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Kevin Peng <kevinp@marvell.com>
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|
| b4121bfb | 09-Oct-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
pl011: prevent putc() and flush() function from blocking indefinitely
It may happen that trace functions are called by OP-TEE when the UART
or its clock is disabled by the non-secure OS. In such a c
pl011: prevent putc() and flush() function from blocking indefinitely
It may happen that trace functions are called by OP-TEE when the UART
or its clock is disabled by the non-secure OS. In such a case, flush()
is likely to loop indefinitely, because the UART status register may
never contain the expected value. Make the code more robust by checking
if the UART is enabled in the wait loop. If it is not, or if the status
bit remains zero due to the clock being turned off, return immediately.
By doing so, we allow to drop some output rather than hang the whole
system.
Fixes: https://github.com/OP-TEE/optee_os/issues/1863
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| d1ee5145 | 03-Oct-2017 |
Peng Fan <peng.fan@nxp.com> |
core: drivers: add imx wdog support
Introducing the wdog support is for psci reset usage.
To i.MX6/7, when `reboot`, need wdog to trigger soc reset
or send out signal to pmic through wdog pin to tri
core: drivers: add imx wdog support
Introducing the wdog support is for psci reset usage.
To i.MX6/7, when `reboot`, need wdog to trigger soc reset
or send out signal to pmic through wdog pin to trigger pmic reset.
In linux device tree, there is a "fsl,ext-reset-output" property, this
driver is to check whether the wdog node contains the property or not,
then decide how to trigger reset.
We still rely on normal world to initialize wdog and configure pinmux
when need to trigger pmic reset.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| cd12a61e | 19-Apr-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
TUI: remove frame buffer
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> |
| a5183a11 | 19-Apr-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
TUI: remove ps2mouse
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 3e6bcc8d | 19-Apr-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
TUI: remove clcd pl111
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 8ce0a099 | 19-Apr-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
TUI: remove PL050
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> |
| e20d1bce | 15-May-2017 |
Akshay Bhat <akshay.bhat@timesys.com> |
plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board
Add basic support to get op-tee to run on SAMA5D2-XULT board.
The SoC is based on single core ARM Cortex-A5 and supports:
ARM TrustZone
plat-sam: Add support for Atmel-Microchip SAMA5D2-XULT board
Add basic support to get op-tee to run on SAMA5D2-XULT board.
The SoC is based on single core ARM Cortex-A5 and supports:
ARM TrustZone with support for configuring memory/peripherals as secure
Secure RTC
Secure boot
On-the-fly encryption/decryption of DDR bus
Tamper protection
Link: http://www.atmel.com/Images/Atmel-11267-32-bit-Cortex-A5-Microcontroller-SAMA5D2_Datasheet.pdf
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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|
| 65d34b1f | 06-Jul-2017 |
Joseph Chen <chenjh@rock-chips.com> |
drivers: serial8250_uart: use 32-bit accesses to the uart registers
Due to hardware design, some platforms can't access the peripheral IO
registers once a byte(8-bit) but once a word(32-bit). Obviou
drivers: serial8250_uart: use 32-bit accesses to the uart registers
Due to hardware design, some platforms can't access the peripheral IO
registers once a byte(8-bit) but once a word(32-bit). Obviously, using
32-bit accesses to the registers is more flexible for other plaforms
to use serial8250 uart.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Igor Opaniuk <igor.opaniuk@linaro.org> (serial8250_uart, TI-AM57xx)
show more ...
|
| c6ac89bc | 18-Jul-2017 |
Peng Fan <peng.fan@nxp.com> |
drivers: add snvs srtc support
Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabili
drivers: add snvs srtc support
Introduce i.MX SNVS SRTC support. The SRTC works with 32.768KHz.
The SRTC is in SNVS_LP domain. The SNVS_LP is a data storage
subsystem with enhanced security capabilities. Its purpose is to store
and protect system data, regardless of the main system power state.
SNVS_LP is in the always-powered-up domain, which is a separate power
domain with its own power supply. When the chip power supply domain
loses power, SNVS_LP continues to operate normally.
Since OP-TEE does not care about calendar time, there is no need
to update calendar time, we only need to read the counter and
get out the time.
The plat_prng_add_jitter_entropy is reused from tee_time_arm_cntpct.c.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 4c56bf5f | 07-Jun-2017 |
Peng Fan <peng.fan@nxp.com> |
drivers: tzc380: add tzc380 driver
Add tzc380 driver support.
The usage:
Use tzc_init(vaddr_t base) to get the tzc380 configuration.
Use tzc_configure_region to configure the memory region,
such as
drivers: tzc380: add tzc380 driver
Add tzc380 driver support.
The usage:
Use tzc_init(vaddr_t base) to get the tzc380 configuration.
Use tzc_configure_region to configure the memory region,
such as "tzc_configure_region(5, 0x4e000000,
TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | TZC_ATTR_REGION_EN_MASK |
TZC_ATTR_SP_S_RW);"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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|
| 440e2223 | 03-May-2017 |
David Wang <david.wang@arm.com> |
The other bits in GICD_CTLR should not be touched
The gic_init() function enables secure and non-secure group1
interrupts in GICD_CTLR register. But the other bits should
not be modified to avoid `U
The other bits in GICD_CTLR should not be touched
The gic_init() function enables secure and non-secure group1
interrupts in GICD_CTLR register. But the other bits should
not be modified to avoid `UNPREDICTABLE` behaviours as per ARM
GICv3 specification.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: minor edits to commit message]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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|
| ddf45954 | 02-Mar-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
pl011: dt: Add DT support
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro
pl011: dt: Add DT support
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|
| 18901324 | 05-Apr-2017 |
David Wang <david.wang@arm.com> |
Support ARM GICv3 mode
In ARM GICv3 mode, the interrupts are used as below for optee_os.
* FIQ - Foreign interrupts not handled by optee_os. This includes
the non-secure interrupts that should be ha
Support ARM GICv3 mode
In ARM GICv3 mode, the interrupts are used as below for optee_os.
* FIQ - Foreign interrupts not handled by optee_os. This includes
the non-secure interrupts that should be handled by the REE and the
secure interrupts assigned to the monitor (aarch32 Monitor mode or
aarch64 EL3).
* IRQ - Native interrupts for optee_os.
And optee_os should use the system register interface to access the GICC
registers in GICv3 mode.
A new build flag `CFG_ARM_GICV3=y` should be set to support GICv3 mode.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 3b3a4611 | 03-Mar-2017 |
Mathieu Briand <mbriand@witekio.com> |
core: arm: Do not handle unsupported interrupts
Trying to handle an interrupt with an ID above the maximum will result
in a kernel panic as the itr_handle() function will try to disable this
unhand
core: arm: Do not handle unsupported interrupts
Trying to handle an interrupt with an ID above the maximum will result
in a kernel panic as the itr_handle() function will try to disable this
unhandled interruption.
Interrupts with a high ID will now be simply ignored.
Signed-off-by: Mathieu Briand <mbriand@witekio.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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|
| 794b6437 | 04-Apr-2017 |
Volodymyr Babchuk <vlad.babchuk@gmail.com> |
drivers: scif: enable TX during initialization
Newer version of TF disables TX and RX modules of SCIF before
jumping to OP-TEE. We need to enable TX back.
Signed-off-by: Volodymyr Babchuk <vlad.bab
drivers: scif: enable TX during initialization
Newer version of TF disables TX and RX modules of SCIF before
jumping to OP-TEE. We need to enable TX back.
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 0cb71d15 | 03-Apr-2017 |
Etienne Carriere <etienne.carriere@st.com> |
core: move plat-stm consoles to generic console framework
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| 39e661bc | 03-Apr-2017 |
Etienne Carriere <etienne.carriere@st.com> |
core: move stih UART driver to the drivers/ directory
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> |
| 8d94060a | 31-Mar-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: fix console drivers against pager
Console operations structures must be kept in the unpaged sections
when pager is enable.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Review
core: fix console drivers against pager
Console operations structures must be kept in the unpaged sections
when pager is enable.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (qemu_virt)
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|
| 0abbda6e | 17-Feb-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
drivers: convert scif_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne
drivers: convert scif_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 2e5aa31b | 17-Feb-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
drivers: convert ns16550 driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne C
drivers: convert ns16550 driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| ab806dc3 | 17-Feb-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
drivers: convert sunxi_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienn
drivers: convert sunxi_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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|
| 59cfa779 | 17-Feb-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
drivers: convert sprd_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne
drivers: convert sprd_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| d66fa083 | 17-Feb-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
drivers: convert serial8250_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: E
drivers: convert serial8250_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
|
| 62fff454 | 17-Feb-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
drivers: convert cdns_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne
drivers: convert cdns_uart driver to use struct serial_chip
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
show more ...
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