| f73055a1 | 28-Mar-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: improve the access of variables in "at91_pm_data"
Flush the TLB before accessing variables in "at91_pm_data". Preload the variables before using.
Signed-off-by: Tony Han <tony.han
drivers: pm: sam: improve the access of variables in "at91_pm_data"
Flush the TLB before accessing variables in "at91_pm_data". Preload the variables before using.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9ba91637 | 28-Mar-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode
Add the header file "sama7-ddr.h" for sama7g5 DRAM controller. Add 2 macros for enable and disable sama7g5 DRAM self-refr
drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode
Add the header file "sama7-ddr.h" for sama7g5 DRAM controller. Add 2 macros for enable and disable sama7g5 DRAM self-refresh mode. Enable self-refresh mode before entering the low-power modes and disable it after exiting the low-power modes.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 6ea2ed2a | 26-Mar-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: add code for sama7g5 LPM (Low-power Mode) pad
Set LPM pad high/low through SHDW_CR register.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklan
drivers: pm: sam: add code for sama7g5 LPM (Low-power Mode) pad
Set LPM pad high/low through SHDW_CR register.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 735a1eff | 28-Mar-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: add code for save/restore sama7g5 MCK1..4 settings
Add 2 macros for save and restore sama7g5 MCK1..4 settings. Save MCK1..4 settings before entering the low-power modes and restore
drivers: pm: sam: add code for save/restore sama7g5 MCK1..4 settings
Add 2 macros for save and restore sama7g5 MCK1..4 settings. Save MCK1..4 settings before entering the low-power modes and restore the settings after exiting the low-power modes. During the low-power mode MCK1..4 use CSS=MAINCK and DIV=1.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b22418eb | 26-Mar-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: add support for checking sama7g5 MCK1..4 ready
sama5d2 has only MCK0 clock. sama7g5 has MCK0,1,..., MCK4 clocks.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wi
drivers: pm: sam: add support for checking sama7g5 MCK1..4 ready
sama5d2 has only MCK0 clock. sama7g5 has MCK0,1,..., MCK4 clocks.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 6d792c58 | 11-Apr-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: update the count of PCK clock for sama7g5
Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks and for sama5d2 there're 4 PCK clocks.
Signed-off-by: Tony Han <ton
drivers: pm: sam: update the count of PCK clock for sama7g5
Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks and for sama5d2 there're 4 PCK clocks.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9a974572 | 07-Apr-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: configure the wakeup sources for sama7g5
Rename the names of functions for adding the configuration of sama7g5 wakeup sources. Add and configure the wakeup sources for sama7g5.
Si
drivers: pm: sam: configure the wakeup sources for sama7g5
Rename the names of functions for adding the configuration of sama7g5 wakeup sources. Add and configure the wakeup sources for sama7g5.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 22b10ee0 | 11-Apr-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: change memory area type to coherent for mapping SRAM
Mapping with memory area type MEM_AREA_TEE_RAM would enable cacheable attribute, it might cause abort in same cases. Here chang
drivers: pm: sam: change memory area type to coherent for mapping SRAM
Mapping with memory area type MEM_AREA_TEE_RAM would enable cacheable attribute, it might cause abort in same cases. Here change the memory area type to MEM_AREA_TEE_COHERENT to map SRAM with non-cacheable attribute to avoid the aborts in the low-power process.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 6e4bc5d9 | 28-Mar-2024 |
Tony Han <tony.han@microchip.com> |
drivers: pm: sam: map SFRBU with DT_MAP_SECURE attribute for sama7g5
As sama7g5's SFRBU is always secured map it as secured and do not need to configure the security through the matrix.
Signed-off-
drivers: pm: sam: map SFRBU with DT_MAP_SECURE attribute for sama7g5
As sama7g5's SFRBU is always secured map it as secured and do not need to configure the security through the matrix.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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