drivers: crypto: stm32: move context allocation/free functions

Move cipher context allocation and free functions to place them
next to each other for CRYP and SAES support to ease their maintenance

drivers: crypto: stm32: move context allocation/free functions

Move cipher context allocation and free functions to place them
next to each other for CRYP and SAES support to ease their maintenance
as the context free sequence is the counter part of the context
allocation sequence. No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss

drivers: crypto: stm32: clean function references

Remove useless & operator in function references of stm32 crypto drivers.
No functional changes.

Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

driver: crypto: hisilicon: fix error handling

When qm_set_vft_common() fails to configure, qm_set_xqc_vft() is
called with the num argument as zero to disable the device. Update
qm_set_xqc_vft() to

driver: crypto: hisilicon: fix error handling

When qm_set_vft_common() fails to configure, qm_set_xqc_vft() is
called with the num argument as zero to disable the device. Update
qm_set_xqc_vft() to handle this error path.

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: se050: fix default configuration for the SE applet

Invalid character was merged in the fixed commit.

Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet")
Sig

drivers: se050: fix default configuration for the SE applet

Invalid character was merged in the fixed commit.

Fixes: fb559031c25f ("drivers: se050: allow configuring the Secure Element applet")
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests i

drivers: crypto: stm32: fix SAES key selection

Correction selection of key in STM32 SAES driver that missed a
left bit shift operation. The bug was not experienced before as
current platform tests involve only the software key selection
(_SAES_CR_KEYSEL_SOFT) which value is 0 and matches the SoC default
key selection register value.

Fixes: 4320f5cf30c5 ("crypto: stm32: SAES cipher support")
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

driver: crypto: hisilicon: update qm init configs

1. add qm_disable_clock_gate for QM_HW_V3
2. set doorbell timeout to QM_DB_TIMEOUT_SET ns

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: J

driver: crypto: hisilicon: update qm init configs

1. add qm_disable_clock_gate for QM_HW_V3
2. set doorbell timeout to QM_DB_TIMEOUT_SET ns

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: caam: sm2 operation fallback

Fallback to software operations for SM2.

Reverts the temporary solution implemented in commit '3489781e9072
("drivers: caam: disable CFG_CRYPTO_SM2_* when ECC

drivers: caam: sm2 operation fallback

Fallback to software operations for SM2.

Reverts the temporary solution implemented in commit '3489781e9072
("drivers: caam: disable CFG_CRYPTO_SM2_* when ECC CAAM driver is
enabled")'.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

show more ...

drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms

The SECO firmware enables the RNG prediction resistance by default.
There is no need to read the CAAM RNG status registers.

Signe

drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms

The SECO firmware enables the RNG prediction resistance by default.
There is no need to read the CAAM RNG status registers.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

show more ...

driver: crypto: hisilicon: Fix temporary memory risk

When the mailbox operation times out, the software will
free the temporary memory. The hardware does not cancel
the mailbox operation and may con

driver: crypto: hisilicon: Fix temporary memory risk

When the mailbox operation times out, the software will
free the temporary memory. The hardware does not cancel
the mailbox operation and may continue to read and write
the free memory.
To solve the problem, we alloc buffer which has the same
lifecycle with qm.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

drivers: caam: Fix for TLS1.3 handshake failure

There is a limitation on some of i.MX8M series platforms.
When the input is marked as a hash value, it is moved first into
the Class 2 Context Registe

drivers: caam: Fix for TLS1.3 handshake failure

There is a limitation on some of i.MX8M series platforms.
When the input is marked as a hash value, it is moved first into
the Class 2 Context Register, which is only 40 bytes long.
From there, it is copied into the PKHA.
If HASH is more than 40bytes, extra bytes become zero, which is not
proper message representative,so signatures generation/verification
go wrong.

This makes a limitation when the hash size is longer than 40 bytes
and the signature component/private key size is longer than 40 bytes
As a workaround when the input is marked as a message representative,
then a different path is taken to bring the value into CAAM,
and the value stays intact.

CFG_NXP_CAAM_C2_CTX_REG_WA config flag is added to enable/disable
this workaround.
Currently it is enabled by default for i.MX8M platforms.

Fixes: 4b383f736e9e ("drivers: caam: implement NXP CAAM Driver - DSA")
Fixes: 503b5c013761 ("drivers: caam: implement NXP CAAM Driver - ECC")
Link: https://github.com/OP-TEE/optee_os/issues/6492
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

drivers: caam: add msg_type argument in DSA_SIGN/VERIFY macro

Add msg_type argument in DSA_SIGN/VERIFY macro.
Based on type of Message whether HASHED, Message representative, will
pass this argument

drivers: caam: add msg_type argument in DSA_SIGN/VERIFY macro

Add msg_type argument in DSA_SIGN/VERIFY macro.
Based on type of Message whether HASHED, Message representative, will
pass this argument.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

driver: crypto: hisilicon: Add the mailbox operation lock

refactor function of mailbox operation to ensure atomaticity

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) modul

driver: crypto: hisilicon: Add the mailbox operation lock

refactor function of mailbox operation to ensure atomaticity

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

drivers: caam: provide plat_rng_init if CFG_WITH_SOFTWARE_PRNG=y

With CFG_NXP_CAAM_RNG_DRV enabled, OP-TEE will use the CAAM
to generate random numbers. Normal world access to the RNG is still
possi

drivers: caam: provide plat_rng_init if CFG_WITH_SOFTWARE_PRNG=y

With CFG_NXP_CAAM_RNG_DRV enabled, OP-TEE will use the CAAM
to generate random numbers. Normal world access to the RNG is still
possible as the CAAM is TrustZone aware and provides multiple separate
job rings.

For complete isolation, however, access to CAAM reset and clocks need to
be managed as well. This could be done in theory by restricting access
to the reset and clock controller peripherals to the secure world and
exporting limited access to some resources via SCMI. There is no such
support yet for the i.MX and thus some setups may prefer to avoid using
the CAAM in OP-TEE to stay safe from normal world inducing glitches.

These setups may still need random numbers in OP-TEE. Therefore, access
so have them
access the CAAM only once at startup to initialize OP-TEE's PRNG and
defer subsequent use of the CAAM to the normal world, whenever
CFG_WITH_SOFTWARE_PRNG=y.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

show more ...

drivers: caam: rng: enable prediction resistance if possible

OP-TEE sets the PR bit on shared descriptors since commit 4ff2ce818e56
("drivers: caam: instantiate RNG state handle with prediction resi

drivers: caam: rng: enable prediction resistance if possible

OP-TEE sets the PR bit on shared descriptors since commit 4ff2ce818e56
("drivers: caam: instantiate RNG state handle with prediction resistance"),
but did not make use of it for random number generation with the reason
explained inside the commit message:

Note: current patch does not deal with RNG state handles that have
already been initialized, but without PR support (this could happen if
U-boot would run before OP-TEE etc.). In this case, RNG state handle
would have to be deinstantiated first, and then reinstantiated with
PR support.

There is a simpler workaround than deinstantiation however: Check if the
state handles have been initialized with prediction resistance (whether
from OP-TEE or outside) and if they were, just set the prediction
resistance bit.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

show more ...

drivers: caam: support querying whether prediction resistance was setup

CAAM shared descriptors initialization may happen inside OP-TEE or
beforehand, either in the bootloader or system controller.

drivers: caam: support querying whether prediction resistance was setup

CAAM shared descriptors initialization may happen inside OP-TEE or
beforehand, either in the bootloader or system controller.

As it's not known at compile-time whether the shared descriptors were
initialized with prediction resistance or not, OP-TEE use of the CAAM
for random number generation omitted requesting prediction resistance.

In preparation for changing that, provide a caam_hal_rng_pr_enabled()
function that queries the state of the PR bits in the shared descriptors.

Reviewed-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

show more ...

driver: crypto: hisilicon: fix an issue of multiple tasks using the same qp

Flag in the qp structure is used to indicate whether
the qp is occupied.The new task can find an unused qp
and use it.

Fi

driver: crypto: hisilicon: fix an issue of multiple tasks using the same qp

Flag in the qp structure is used to indicate whether
the qp is occupied.The new task can find an unused qp
and use it.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jer

drivers: caam: update return type of caam_sm_free()

Update return type of caam_sm_free() from TEE_Result
to enum caam_status.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

show more ...

drivers: crypto: hisilicon: fix QM cache start and done define

Address offset of qm_cache_wb_start and qm_cache_wb_done
is wrong.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management

drivers: crypto: hisilicon: fix QM cache start and done define

Address offset of qm_cache_wb_start and qm_cache_wb_done
is wrong.

Fixes: c7f9abcee87f ("drivers: implement HiSilicon Queue Management (QM) module")
Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
[Edit commit subject]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

drivers: implement HiSilicon Queue Management (QM) module

The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management

drivers: implement HiSilicon Queue Management (QM) module

The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management module QM is used to interact with software.
Each accelerator module integrates a QM. Software issues tasks to the SQ
(Submmision Queue),and the QM obtains the address of the SQE (Submmision
Queue Element). The BD (Buffer Description, same as SQE) information is
sent to the accelerator. After the task processing is complete, the
accelerator applies for a write-back address from the QM to write back
the SQ.

Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

tree-wide: remove useless newline character in *MSG() messages

The *MSG() macros take care of printing a newline. Adding a newline
character ('\n') is useless. Remove it.

Signed-off-by: Vincent Mai

tree-wide: remove useless newline character in *MSG() messages

The *MSG() macros take care of printing a newline. Adding a newline
character ('\n') is useless. Remove it.

Signed-off-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

drivers: crypto: caam: fix job ring interruption number

The job ring interruption number is 356 for job ring 3.

Fixes: b21f12209671 ("drivers: crypto: caam: use job ring 3 on i.mx8dxlevk")
Signed-o

drivers: crypto: caam: fix job ring interruption number

The job ring interruption number is 356 for job ring 3.

Fixes: b21f12209671 ("drivers: crypto: caam: use job ring 3 on i.mx8dxlevk")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

drivers: crypto: caam: use job ring 3 on i.mx8dxlevk

Use the job ring #3 on i.mx8dxl to avoid resource conflict with other
software stacks.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acke

drivers: crypto: caam: use job ring 3 on i.mx8dxlevk

Use the job ring #3 on i.mx8dxl to avoid resource conflict with other
software stacks.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

drivers: crypto: caam: upgrade to new interrupt framework

Moves CAAM job ring driver to the new interrupt framework API functions.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off

drivers: crypto: caam: upgrade to new interrupt framework

Moves CAAM job ring driver to the new interrupt framework API functions.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

drivers: caam: remove unnecessary header file

Remove #include <caam_utils_status.h>

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: crypto: stm32: lower verbosity on SAES use

Changes SAES context allocation/release trace message from debug level
to flow level otherwise each access to the secure storage emits debug
messa

drivers: crypto: stm32: lower verbosity on SAES use

Changes SAES context allocation/release trace message from debug level
to flow level otherwise each access to the secure storage emits debug
messages.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...