1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 #ifndef __MM_CORE_MMU_H 7 #define __MM_CORE_MMU_H 8 9 #ifndef __ASSEMBLER__ 10 #include <assert.h> 11 #include <compiler.h> 12 #include <kernel/user_ta.h> 13 #include <mm/tee_mmu_types.h> 14 #include <types_ext.h> 15 #include <util.h> 16 #endif 17 18 #include <mm/core_mmu_arch.h> 19 #include <platform_config.h> 20 21 /* A small page is the smallest unit of memory that can be mapped */ 22 #define SMALL_PAGE_SIZE BIT(SMALL_PAGE_SHIFT) 23 #define SMALL_PAGE_MASK ((paddr_t)SMALL_PAGE_SIZE - 1) 24 25 /* 26 * PGDIR is the translation table above the translation table that holds 27 * the pages. 28 */ 29 #define CORE_MMU_PGDIR_SIZE BIT(CORE_MMU_PGDIR_SHIFT) 30 #define CORE_MMU_PGDIR_MASK ((paddr_t)CORE_MMU_PGDIR_SIZE - 1) 31 32 /* TA user space code, data, stack and heap are mapped using this granularity */ 33 #define CORE_MMU_USER_CODE_SIZE BIT(CORE_MMU_USER_CODE_SHIFT) 34 #define CORE_MMU_USER_CODE_MASK ((paddr_t)CORE_MMU_USER_CODE_SIZE - 1) 35 36 /* TA user space parameters are mapped using this granularity */ 37 #define CORE_MMU_USER_PARAM_SIZE BIT(CORE_MMU_USER_PARAM_SHIFT) 38 #define CORE_MMU_USER_PARAM_MASK ((paddr_t)CORE_MMU_USER_PARAM_SIZE - 1) 39 40 /* 41 * Identify mapping constraint: virtual base address is the physical start addr. 42 * If platform did not set some macros, some get default value. 43 */ 44 #ifndef TEE_RAM_VA_SIZE 45 #define TEE_RAM_VA_SIZE CORE_MMU_PGDIR_SIZE 46 #endif 47 48 #ifndef TEE_LOAD_ADDR 49 #define TEE_LOAD_ADDR TEE_RAM_START 50 #endif 51 52 #ifndef STACK_ALIGNMENT 53 #define STACK_ALIGNMENT (sizeof(long) * U(2)) 54 #endif 55 56 #ifndef __ASSEMBLER__ 57 /* 58 * Memory area type: 59 * MEM_AREA_END: Reserved, marks the end of a table of mapping areas. 60 * MEM_AREA_TEE_RAM: core RAM (read/write/executable, secure, reserved to TEE) 61 * MEM_AREA_TEE_RAM_RX: core private read-only/executable memory (secure) 62 * MEM_AREA_TEE_RAM_RO: core private read-only/non-executable memory (secure) 63 * MEM_AREA_TEE_RAM_RW: core private read/write/non-executable memory (secure) 64 * MEM_AREA_INIT_RAM_RO: init private read-only/non-executable memory (secure) 65 * MEM_AREA_INIT_RAM_RX: init private read-only/executable memory (secure) 66 * MEM_AREA_NEX_RAM_RO: nexus private read-only/non-executable memory (secure) 67 * MEM_AREA_NEX_RAM_RW: nexus private r/w/non-executable memory (secure) 68 * MEM_AREA_TEE_COHERENT: teecore coherent RAM (secure, reserved to TEE) 69 * MEM_AREA_TEE_ASAN: core address sanitizer RAM (secure, reserved to TEE) 70 * MEM_AREA_IDENTITY_MAP_RX: core identity mapped r/o executable memory (secure) 71 * MEM_AREA_TA_RAM: Secure RAM where teecore loads/exec TA instances. 72 * MEM_AREA_NSEC_SHM: NonSecure shared RAM between NSec and TEE. 73 * MEM_AREA_NEX_NSEC_SHM: nexus non-secure shared RAM between NSec and TEE. 74 * MEM_AREA_RAM_NSEC: NonSecure RAM storing data 75 * MEM_AREA_RAM_SEC: Secure RAM storing some secrets 76 * MEM_AREA_IO_NSEC: NonSecure HW mapped registers 77 * MEM_AREA_IO_SEC: Secure HW mapped registers 78 * MEM_AREA_EXT_DT: Memory loads external device tree 79 * MEM_AREA_MANIFEST_DT: Memory loads manifest device tree 80 * MEM_AREA_TRANSFER_LIST: Memory area mapped for Transfer List 81 * MEM_AREA_RES_VASPACE: Reserved virtual memory space 82 * MEM_AREA_SHM_VASPACE: Virtual memory space for dynamic shared memory buffers 83 * MEM_AREA_TS_VASPACE: TS va space, only used with phys_to_virt() 84 * MEM_AREA_DDR_OVERALL: Overall DDR address range, candidate to dynamic shm. 85 * MEM_AREA_SEC_RAM_OVERALL: Whole secure RAM 86 * MEM_AREA_MAXTYPE: lower invalid 'type' value 87 */ 88 enum teecore_memtypes { 89 MEM_AREA_END = 0, 90 MEM_AREA_TEE_RAM, 91 MEM_AREA_TEE_RAM_RX, 92 MEM_AREA_TEE_RAM_RO, 93 MEM_AREA_TEE_RAM_RW, 94 MEM_AREA_INIT_RAM_RO, 95 MEM_AREA_INIT_RAM_RX, 96 MEM_AREA_NEX_RAM_RO, 97 MEM_AREA_NEX_RAM_RW, 98 MEM_AREA_TEE_COHERENT, 99 MEM_AREA_TEE_ASAN, 100 MEM_AREA_IDENTITY_MAP_RX, 101 MEM_AREA_TA_RAM, 102 MEM_AREA_NSEC_SHM, 103 MEM_AREA_NEX_NSEC_SHM, 104 MEM_AREA_RAM_NSEC, 105 MEM_AREA_RAM_SEC, 106 MEM_AREA_IO_NSEC, 107 MEM_AREA_IO_SEC, 108 MEM_AREA_EXT_DT, 109 MEM_AREA_MANIFEST_DT, 110 MEM_AREA_TRANSFER_LIST, 111 MEM_AREA_RES_VASPACE, 112 MEM_AREA_SHM_VASPACE, 113 MEM_AREA_TS_VASPACE, 114 MEM_AREA_PAGER_VASPACE, 115 MEM_AREA_SDP_MEM, 116 MEM_AREA_DDR_OVERALL, 117 MEM_AREA_SEC_RAM_OVERALL, 118 MEM_AREA_MAXTYPE 119 }; 120 121 static inline const char *teecore_memtype_name(enum teecore_memtypes type) 122 { 123 static const char * const names[] = { 124 [MEM_AREA_END] = "END", 125 [MEM_AREA_TEE_RAM] = "TEE_RAM_RWX", 126 [MEM_AREA_TEE_RAM_RX] = "TEE_RAM_RX", 127 [MEM_AREA_TEE_RAM_RO] = "TEE_RAM_RO", 128 [MEM_AREA_TEE_RAM_RW] = "TEE_RAM_RW", 129 [MEM_AREA_INIT_RAM_RO] = "INIT_RAM_RO", 130 [MEM_AREA_INIT_RAM_RX] = "INIT_RAM_RX", 131 [MEM_AREA_NEX_RAM_RO] = "NEX_RAM_RO", 132 [MEM_AREA_NEX_RAM_RW] = "NEX_RAM_RW", 133 [MEM_AREA_TEE_ASAN] = "TEE_ASAN", 134 [MEM_AREA_IDENTITY_MAP_RX] = "IDENTITY_MAP_RX", 135 [MEM_AREA_TEE_COHERENT] = "TEE_COHERENT", 136 [MEM_AREA_TA_RAM] = "TA_RAM", 137 [MEM_AREA_NSEC_SHM] = "NSEC_SHM", 138 [MEM_AREA_NEX_NSEC_SHM] = "NEX_NSEC_SHM", 139 [MEM_AREA_RAM_NSEC] = "RAM_NSEC", 140 [MEM_AREA_RAM_SEC] = "RAM_SEC", 141 [MEM_AREA_IO_NSEC] = "IO_NSEC", 142 [MEM_AREA_IO_SEC] = "IO_SEC", 143 [MEM_AREA_EXT_DT] = "EXT_DT", 144 [MEM_AREA_MANIFEST_DT] = "MANIFEST_DT", 145 [MEM_AREA_TRANSFER_LIST] = "TRANSFER_LIST", 146 [MEM_AREA_RES_VASPACE] = "RES_VASPACE", 147 [MEM_AREA_SHM_VASPACE] = "SHM_VASPACE", 148 [MEM_AREA_TS_VASPACE] = "TS_VASPACE", 149 [MEM_AREA_PAGER_VASPACE] = "PAGER_VASPACE", 150 [MEM_AREA_SDP_MEM] = "SDP_MEM", 151 [MEM_AREA_DDR_OVERALL] = "DDR_OVERALL", 152 [MEM_AREA_SEC_RAM_OVERALL] = "SEC_RAM_OVERALL", 153 }; 154 155 COMPILE_TIME_ASSERT(ARRAY_SIZE(names) == MEM_AREA_MAXTYPE); 156 return names[type]; 157 } 158 159 #ifdef CFG_CORE_RWDATA_NOEXEC 160 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM_RW 161 #else 162 #define MEM_AREA_TEE_RAM_RW_DATA MEM_AREA_TEE_RAM 163 #endif 164 165 struct core_mmu_phys_mem { 166 const char *name; 167 enum teecore_memtypes type; 168 __extension__ union { 169 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 170 struct { 171 uint32_t lo_addr; 172 uint32_t hi_addr; 173 }; 174 #endif 175 paddr_t addr; 176 }; 177 __extension__ union { 178 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 179 struct { 180 uint32_t lo_size; 181 uint32_t hi_size; 182 }; 183 #endif 184 paddr_size_t size; 185 }; 186 }; 187 188 #define __register_memory(_name, _type, _addr, _size, _section) \ 189 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 190 { .name = (_name), .type = (_type), .addr = (_addr), \ 191 .size = (_size) } 192 193 #if __SIZEOF_LONG__ != __SIZEOF_PADDR__ 194 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 195 SCATTERED_ARRAY_DEFINE_ITEM(_section, struct core_mmu_phys_mem) = \ 196 { .name = (_name), .type = (_type), .lo_addr = (_addr), \ 197 .lo_size = (_size) } 198 #else 199 #define __register_memory_ul(_name, _type, _addr, _size, _section) \ 200 __register_memory(_name, _type, _addr, _size, _section) 201 #endif 202 203 #define register_phys_mem(type, addr, size) \ 204 __register_memory(#addr, (type), (addr), (size), \ 205 phys_mem_map) 206 207 #define register_phys_mem_ul(type, addr, size) \ 208 __register_memory_ul(#addr, (type), (addr), (size), \ 209 phys_mem_map) 210 211 /* Same as register_phys_mem() but with PGDIR_SIZE granularity */ 212 #define register_phys_mem_pgdir(type, addr, size) \ 213 __register_memory(#addr, type, ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 214 ROUNDUP(size + addr - \ 215 ROUNDDOWN(addr, CORE_MMU_PGDIR_SIZE), \ 216 CORE_MMU_PGDIR_SIZE), phys_mem_map) 217 218 #ifdef CFG_SECURE_DATA_PATH 219 #define register_sdp_mem(addr, size) \ 220 __register_memory(#addr, MEM_AREA_SDP_MEM, (addr), (size), \ 221 phys_sdp_mem) 222 #else 223 #define register_sdp_mem(addr, size) \ 224 static int CONCAT(__register_sdp_mem_unused, __COUNTER__) \ 225 __unused 226 #endif 227 228 /* register_dynamic_shm() is deprecated, please use register_ddr() instead */ 229 #define register_dynamic_shm(addr, size) \ 230 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), (size), \ 231 phys_ddr_overall_compat) 232 233 /* 234 * register_ddr() - Define a memory range 235 * @addr: Base address 236 * @size: Length 237 * 238 * This macro can be used multiple times to define disjoint ranges. While 239 * initializing holes are carved out of these ranges where it overlaps with 240 * special memory, for instance memory registered with register_sdp_mem(). 241 * 242 * The memory that remains is accepted as non-secure shared memory when 243 * communicating with normal world. 244 * 245 * This macro is an alternative to supply the memory description with a 246 * devicetree blob. 247 */ 248 #define register_ddr(addr, size) \ 249 __register_memory(#addr, MEM_AREA_DDR_OVERALL, (addr), \ 250 (size), phys_ddr_overall) 251 252 #define phys_ddr_overall_begin \ 253 SCATTERED_ARRAY_BEGIN(phys_ddr_overall, struct core_mmu_phys_mem) 254 255 #define phys_ddr_overall_end \ 256 SCATTERED_ARRAY_END(phys_ddr_overall, struct core_mmu_phys_mem) 257 258 #define phys_ddr_overall_compat_begin \ 259 SCATTERED_ARRAY_BEGIN(phys_ddr_overall_compat, struct core_mmu_phys_mem) 260 261 #define phys_ddr_overall_compat_end \ 262 SCATTERED_ARRAY_END(phys_ddr_overall_compat, struct core_mmu_phys_mem) 263 264 #define phys_sdp_mem_begin \ 265 SCATTERED_ARRAY_BEGIN(phys_sdp_mem, struct core_mmu_phys_mem) 266 267 #define phys_sdp_mem_end \ 268 SCATTERED_ARRAY_END(phys_sdp_mem, struct core_mmu_phys_mem) 269 270 #define phys_mem_map_begin \ 271 SCATTERED_ARRAY_BEGIN(phys_mem_map, struct core_mmu_phys_mem) 272 273 #define phys_mem_map_end \ 274 SCATTERED_ARRAY_END(phys_mem_map, struct core_mmu_phys_mem) 275 276 #ifdef CFG_CORE_RESERVED_SHM 277 /* Default NSec shared memory allocated from NSec world */ 278 extern unsigned long default_nsec_shm_paddr; 279 extern unsigned long default_nsec_shm_size; 280 #endif 281 282 /* 283 * Physical load address of OP-TEE updated during boot if needed to reflect 284 * the value used. 285 */ 286 #ifdef CFG_CORE_PHYS_RELOCATABLE 287 extern unsigned long core_mmu_tee_load_pa; 288 #else 289 extern const unsigned long core_mmu_tee_load_pa; 290 #endif 291 292 void core_init_mmu_map(unsigned long seed, struct core_mmu_config *cfg); 293 void core_init_mmu_regs(struct core_mmu_config *cfg); 294 295 /* Arch specific function to help optimizing 1 MMU xlat table */ 296 bool core_mmu_prefer_tee_ram_at_top(paddr_t paddr); 297 298 /* 299 * struct mmu_partition - stores MMU partition. 300 * 301 * Basically it represent whole MMU mapping. It is possible 302 * to create multiple partitions, and change them in runtime, 303 * effectively changing how OP-TEE sees memory. 304 * This is opaque struct which is defined differently for 305 * v7 and LPAE MMUs 306 * 307 * This structure used mostly when virtualization is enabled. 308 * When CFG_NS_VIRTUALIZATION==n only default partition exists. 309 */ 310 struct mmu_partition; 311 312 /* 313 * core_mmu_get_user_va_range() - Return range of user va space 314 * @base: Lowest user virtual address 315 * @size: Size in bytes of user address space 316 */ 317 void core_mmu_get_user_va_range(vaddr_t *base, size_t *size); 318 319 /* 320 * enum core_mmu_fault - different kinds of faults 321 * @CORE_MMU_FAULT_ALIGNMENT: alignment fault 322 * @CORE_MMU_FAULT_DEBUG_EVENT: debug event 323 * @CORE_MMU_FAULT_TRANSLATION: translation fault 324 * @CORE_MMU_FAULT_WRITE_PERMISSION: Permission fault during write 325 * @CORE_MMU_FAULT_READ_PERMISSION: Permission fault during read 326 * @CORE_MMU_FAULT_ASYNC_EXTERNAL: asynchronous external abort 327 * @CORE_MMU_FAULT_ACCESS_BIT: access bit fault 328 * @CORE_MMU_FAULT_TAG_CHECK: tag check fault 329 * @CORE_MMU_FAULT_OTHER: Other/unknown fault 330 */ 331 enum core_mmu_fault { 332 CORE_MMU_FAULT_ALIGNMENT, 333 CORE_MMU_FAULT_DEBUG_EVENT, 334 CORE_MMU_FAULT_TRANSLATION, 335 CORE_MMU_FAULT_WRITE_PERMISSION, 336 CORE_MMU_FAULT_READ_PERMISSION, 337 CORE_MMU_FAULT_ASYNC_EXTERNAL, 338 CORE_MMU_FAULT_ACCESS_BIT, 339 CORE_MMU_FAULT_TAG_CHECK, 340 CORE_MMU_FAULT_OTHER, 341 }; 342 343 /* 344 * core_mmu_get_fault_type() - get fault type 345 * @fault_descr: Content of fault status or exception syndrome register 346 * @returns an enum describing the content of fault status register. 347 */ 348 enum core_mmu_fault core_mmu_get_fault_type(uint32_t fault_descr); 349 350 /* 351 * core_mm_type_to_attr() - convert memory type to attribute 352 * @t: memory type 353 * @returns an attribute that can be passed to core_mm_set_entry() and friends 354 */ 355 uint32_t core_mmu_type_to_attr(enum teecore_memtypes t); 356 357 /* 358 * core_mmu_create_user_map() - Create user mode mapping 359 * @uctx: Pointer to user mode context 360 * @map: MMU configuration to use when activating this VA space 361 */ 362 void core_mmu_create_user_map(struct user_mode_ctx *uctx, 363 struct core_mmu_user_map *map); 364 /* 365 * core_mmu_get_user_map() - Reads current MMU configuration for user VA space 366 * @map: MMU configuration for current user VA space. 367 */ 368 void core_mmu_get_user_map(struct core_mmu_user_map *map); 369 370 /* 371 * core_mmu_set_user_map() - Set new MMU configuration for user VA space 372 * @map: User context MMU configuration or NULL to set core VA space 373 * 374 * Activate user VA space mapping and set its ASID if @map is not NULL, 375 * otherwise activate core mapping and set ASID to 0. 376 */ 377 void core_mmu_set_user_map(struct core_mmu_user_map *map); 378 379 /* 380 * struct core_mmu_table_info - Properties for a translation table 381 * @table: Pointer to translation table 382 * @va_base: VA base address of the transaltion table 383 * @level: Translation table level 384 * @next_level: Finer grained translation table level according to @level. 385 * @shift: The shift of each entry in the table 386 * @num_entries: Number of entries in this table. 387 */ 388 struct core_mmu_table_info { 389 void *table; 390 vaddr_t va_base; 391 unsigned num_entries; 392 #ifdef CFG_NS_VIRTUALIZATION 393 struct mmu_partition *prtn; 394 #endif 395 uint8_t level; 396 uint8_t shift; 397 uint8_t next_level; 398 }; 399 400 /* 401 * core_mmu_find_table() - Locates a translation table 402 * @prtn: MMU partition where search should be performed 403 * @va: Virtual address for the table to cover 404 * @max_level: Don't traverse beyond this level 405 * @tbl_info: Pointer to where to store properties. 406 * @return true if a translation table was found, false on error 407 */ 408 bool core_mmu_find_table(struct mmu_partition *prtn, vaddr_t va, 409 unsigned max_level, 410 struct core_mmu_table_info *tbl_info); 411 412 /* 413 * core_mmu_entry_to_finer_grained() - divide mapping at current level into 414 * smaller ones so memory can be mapped with finer granularity 415 * @tbl_info: table where target record located 416 * @idx: index of record for which a pdgir must be setup. 417 * @secure: true/false if pgdir maps secure/non-secure memory (32bit mmu) 418 * @return true on successful, false on error 419 */ 420 bool core_mmu_entry_to_finer_grained(struct core_mmu_table_info *tbl_info, 421 unsigned int idx, bool secure); 422 423 void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx, 424 paddr_t pa, uint32_t attr); 425 426 void core_mmu_get_user_pgdir(struct core_mmu_table_info *pgd_info); 427 428 /* 429 * core_mmu_set_entry() - Set entry in translation table 430 * @tbl_info: Translation table properties 431 * @idx: Index of entry to update 432 * @pa: Physical address to assign entry 433 * @attr: Attributes to assign entry 434 */ 435 void core_mmu_set_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 436 paddr_t pa, uint32_t attr); 437 438 void core_mmu_get_entry_primitive(const void *table, size_t level, size_t idx, 439 paddr_t *pa, uint32_t *attr); 440 441 /* 442 * core_mmu_get_entry() - Get entry from translation table 443 * @tbl_info: Translation table properties 444 * @idx: Index of entry to read 445 * @pa: Physical address is returned here if pa is not NULL 446 * @attr: Attributues are returned here if attr is not NULL 447 */ 448 void core_mmu_get_entry(struct core_mmu_table_info *tbl_info, unsigned idx, 449 paddr_t *pa, uint32_t *attr); 450 451 /* 452 * core_mmu_va2idx() - Translate from virtual address to table index 453 * @tbl_info: Translation table properties 454 * @va: Virtual address to translate 455 * @returns index in transaltion table 456 */ 457 static inline unsigned core_mmu_va2idx(struct core_mmu_table_info *tbl_info, 458 vaddr_t va) 459 { 460 return (va - tbl_info->va_base) >> tbl_info->shift; 461 } 462 463 /* 464 * core_mmu_idx2va() - Translate from table index to virtual address 465 * @tbl_info: Translation table properties 466 * @idx: Index to translate 467 * @returns Virtual address 468 */ 469 static inline vaddr_t core_mmu_idx2va(struct core_mmu_table_info *tbl_info, 470 unsigned idx) 471 { 472 return (idx << tbl_info->shift) + tbl_info->va_base; 473 } 474 475 /* 476 * core_mmu_get_block_offset() - Get offset inside a block/page 477 * @tbl_info: Translation table properties 478 * @pa: Physical address 479 * @returns offset within one block of the translation table 480 */ 481 static inline size_t core_mmu_get_block_offset( 482 struct core_mmu_table_info *tbl_info, paddr_t pa) 483 { 484 return pa & ((1 << tbl_info->shift) - 1); 485 } 486 487 /* 488 * core_mmu_is_dynamic_vaspace() - Check if memory region belongs to 489 * empty virtual address space that is used for dymanic mappings 490 * @mm: memory region to be checked 491 * @returns result of the check 492 */ 493 static inline bool core_mmu_is_dynamic_vaspace(struct tee_mmap_region *mm) 494 { 495 return mm->type == MEM_AREA_RES_VASPACE || 496 mm->type == MEM_AREA_SHM_VASPACE; 497 } 498 499 /* 500 * core_mmu_map_pages() - map list of pages at given virtual address 501 * @vstart: Virtual address where mapping begins 502 * @pages: Array of page addresses 503 * @num_pages: Number of pages 504 * @memtype: Type of memmory to be mapped 505 * 506 * Note: This function asserts that pages are not mapped executeable for 507 * kernel (privileged) mode. 508 * 509 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 510 */ 511 TEE_Result core_mmu_map_pages(vaddr_t vstart, paddr_t *pages, size_t num_pages, 512 enum teecore_memtypes memtype); 513 514 /* 515 * core_mmu_map_contiguous_pages() - map range of pages at given virtual address 516 * @vstart: Virtual address where mapping begins 517 * @pstart: Physical address of the first page 518 * @num_pages: Number of pages 519 * @memtype: Type of memmory to be mapped 520 * 521 * Note: This function asserts that pages are not mapped executeable for 522 * kernel (privileged) mode. 523 * 524 * @returns: TEE_SUCCESS on success, TEE_ERROR_XXX on error 525 */ 526 TEE_Result core_mmu_map_contiguous_pages(vaddr_t vstart, paddr_t pstart, 527 size_t num_pages, 528 enum teecore_memtypes memtype); 529 530 /* 531 * core_mmu_unmap_pages() - remove mapping at given virtual address 532 * @vstart: Virtual address where mapping begins 533 * @num_pages: Number of pages to unmap 534 */ 535 void core_mmu_unmap_pages(vaddr_t vstart, size_t num_pages); 536 537 /* 538 * core_mmu_user_mapping_is_active() - Report if user mapping is active 539 * @returns true if a user VA space is active, false if user VA space is 540 * inactive. 541 */ 542 bool core_mmu_user_mapping_is_active(void); 543 544 /* 545 * core_mmu_mattr_is_ok() - Check that supplied mem attributes can be used 546 * @returns true if the attributes can be used, false if not. 547 */ 548 bool core_mmu_mattr_is_ok(uint32_t mattr); 549 550 void core_mmu_get_mem_by_type(enum teecore_memtypes type, vaddr_t *s, 551 vaddr_t *e); 552 553 enum teecore_memtypes core_mmu_get_type_by_pa(paddr_t pa); 554 555 /* routines to retreive shared mem configuration */ 556 static inline bool core_mmu_is_shm_cached(void) 557 { 558 return mattr_is_cached(core_mmu_type_to_attr(MEM_AREA_NSEC_SHM)); 559 } 560 561 TEE_Result core_mmu_remove_mapping(enum teecore_memtypes type, void *addr, 562 size_t len); 563 void *core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, 564 size_t len); 565 566 /* 567 * core_mmu_find_mapping_exclusive() - Find mapping of specified type and 568 * length. If more than one mapping of 569 * specified type is present, NULL will be 570 * returned. 571 * @type: memory type 572 * @len: length in bytes 573 */ 574 struct tee_mmap_region * 575 core_mmu_find_mapping_exclusive(enum teecore_memtypes type, size_t len); 576 577 /* 578 * tlbi_va_range() - Invalidate TLB for virtual address range 579 * @va: start virtual address, must be a multiple of @granule 580 * @len: length in bytes of range, must be a multiple of @granule 581 * @granule: granularity of mapping, supported values are 582 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 583 * match the actual mappings. 584 */ 585 void tlbi_va_range(vaddr_t va, size_t len, size_t granule); 586 587 /* 588 * tlbi_va_range_asid() - Invalidate TLB for virtual address range for 589 * a specific ASID 590 * @va: start virtual address, must be a multiple of @granule 591 * @len: length in bytes of range, must be a multiple of @granule 592 * @granule: granularity of mapping, supported values are 593 * CORE_MMU_PGDIR_SIZE or SMALL_PAGE_SIZE. This value must 594 * match the actual mappings. 595 * @asid: Address space identifier 596 */ 597 void tlbi_va_range_asid(vaddr_t va, size_t len, size_t granule, uint32_t asid); 598 599 /* Check cpu mmu enabled or not */ 600 bool cpu_mmu_enabled(void); 601 602 #ifdef CFG_CORE_DYN_SHM 603 /* 604 * Check if platform defines nsec DDR range(s). 605 * Static SHM (MEM_AREA_NSEC_SHM) is not covered by this API as it is 606 * always present. 607 */ 608 bool core_mmu_nsec_ddr_is_defined(void); 609 610 void core_mmu_set_discovered_nsec_ddr(struct core_mmu_phys_mem *start, 611 size_t nelems); 612 #endif 613 614 /* Initialize MMU partition */ 615 void core_init_mmu_prtn(struct mmu_partition *prtn, struct tee_mmap_region *mm); 616 617 unsigned int asid_alloc(void); 618 void asid_free(unsigned int asid); 619 620 #ifdef CFG_SECURE_DATA_PATH 621 /* Alloc and fill SDP memory objects table - table is NULL terminated */ 622 struct mobj **core_sdp_mem_create_mobjs(void); 623 #endif 624 625 #ifdef CFG_NS_VIRTUALIZATION 626 size_t core_mmu_get_total_pages_size(void); 627 struct mmu_partition *core_alloc_mmu_prtn(void *tables); 628 void core_free_mmu_prtn(struct mmu_partition *prtn); 629 void core_mmu_set_prtn(struct mmu_partition *prtn); 630 void core_mmu_set_default_prtn(void); 631 void core_mmu_set_default_prtn_tbl(void); 632 #endif 633 634 void core_mmu_init_virtualization(void); 635 636 /* init some allocation pools */ 637 void core_mmu_init_ta_ram(void); 638 639 void core_init_mmu(struct tee_mmap_region *mm); 640 641 void core_mmu_set_info_table(struct core_mmu_table_info *tbl_info, 642 unsigned int level, vaddr_t va_base, void *table); 643 void core_mmu_populate_user_map(struct core_mmu_table_info *dir_info, 644 struct user_mode_ctx *uctx); 645 void core_mmu_map_region(struct mmu_partition *prtn, 646 struct tee_mmap_region *mm); 647 648 bool arch_va2pa_helper(void *va, paddr_t *pa); 649 650 static inline bool core_mmap_is_end_of_table(const struct tee_mmap_region *mm) 651 { 652 return mm->type == MEM_AREA_END; 653 } 654 655 static inline bool core_mmu_check_end_pa(paddr_t pa, size_t len) 656 { 657 paddr_t end_pa = 0; 658 659 if (ADD_OVERFLOW(pa, len - 1, &end_pa)) 660 return false; 661 return core_mmu_check_max_pa(end_pa); 662 } 663 664 /* 665 * core_mmu_set_secure_memory() - set physical secure memory range 666 * @base: base address of secure memory 667 * @size: size of secure memory 668 * 669 * The physical secure memory range is not known in advance when OP-TEE is 670 * relocatable, this information must be supplied once during boot before 671 * the translation tables can be initialized and the MMU enabled. 672 */ 673 void core_mmu_set_secure_memory(paddr_t base, size_t size); 674 675 /* 676 * core_mmu_get_secure_memory() - get physical secure memory range 677 * @base: base address of secure memory 678 * @size: size of secure memory 679 * 680 * The physical secure memory range returned covers at least the memory 681 * range used by OP-TEE Core, but may cover more memory depending on the 682 * configuration. 683 */ 684 void core_mmu_get_secure_memory(paddr_t *base, paddr_size_t *size); 685 686 /* 687 * core_mmu_get_ta_range() - get physical memory range reserved for TAs 688 * @base: [out] range base address ref or NULL 689 * @size: [out] range size ref or NULL 690 */ 691 void core_mmu_get_ta_range(paddr_t *base, size_t *size); 692 693 #endif /*__ASSEMBLER__*/ 694 695 #endif /* __MM_CORE_MMU_H */ 696