clk: qcom: move PAS clock group to its own compilation unit

PAS clock configuration is conditionally compiled and platform-specific;
keeping it in the same file as the core clock setup adds unnecess

clk: qcom: move PAS clock group to its own compilation unit

PAS clock configuration is conditionally compiled and platform-specific;
keeping it in the same file as the core clock setup adds unnecessary
coupling and complicates maintenance.

No functional change.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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pta: qcom_pas: Add support for ADSP

Add Peripheral Authentication Service (PAS) support for the
Audio DSP (ADSP), enabling loading of the ADSP firmware image.

Authentication not done yet.

Initial

pta: qcom_pas: Add support for ADSP

Add Peripheral Authentication Service (PAS) support for the
Audio DSP (ADSP), enabling loading of the ADSP firmware image.

Authentication not done yet.

Initial validation used https://github.com/qualcomm/fastrpc.git
(all tests pass)

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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pta: qcom_pas: Add support for CDSP

Add Peripheral Authentication Service (PAS) support for the
Compute DSP (CDSP), enabling loading of the CDSP firmware image.

Authentication not done yet.

Initia

pta: qcom_pas: Add support for CDSP

Add Peripheral Authentication Service (PAS) support for the
Compute DSP (CDSP), enabling loading of the CDSP firmware image.

Authentication not done yet.

Initial validation used https://github.com/qualcomm/fastrpc.git
(all tests pass)

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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plat: qcom: kodiak: move clock definitions to platform header

Move Kodiak-specific GCC clock register offsets out of the generic
clock-qcom driver into a platform header.

Introduce clock_group_qcom

plat: qcom: kodiak: move clock definitions to platform header

Move Kodiak-specific GCC clock register offsets out of the generic
clock-qcom driver into a platform header.

Introduce clock_group_qcom.h under platform/kodiak to hold the clock
register offsets required by the driver and update the build system so
the platform include path is visible to the clock driver.

Also move the GCC MMIO mapping from plat-qcom/main.c into the clock
driver. This keeps the mapping local to the driver that consumes the
registers and avoids exposing platform clock registers globally during
platform initialization.

This change is a preparation step to support additional Qualcomm
platforms while keeping the common clock driver platform-agnostic.

No functional change intended.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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clk: Add initial clock framework for Qualcomm platforms

Add clock framework for Qualcomm platforms. Currently the support is
added for clocks related to WPSS subsystem on Kodiak SoC.

Co-developed-b

clk: Add initial clock framework for Qualcomm platforms

Add clock framework for Qualcomm platforms. Currently the support is
added for clocks related to WPSS subsystem on Kodiak SoC.

Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.rammirez@oss.qualcomm.com>

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plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized sta

plat: stm32mp2: sysconf: fix CA35SS register names

Align register names with the reference manuel for Arm Cortex-A35 (CA35SS)
- CA35SS SYSCFG registers (with 0x2000 offset)
- CA35SS Standardized status and control (SSC) registers

This path removes the confusion between SSC and subsystem (SS).

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Co-developed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: cosmetic fixes for STM32MP25 clock driver

Cosmetic fixes to align STM32MP21 and STM32MP25 clock drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by

clk: stm32mp25: cosmetic fixes for STM32MP25 clock driver

Cosmetic fixes to align STM32MP21 and STM32MP25 clock drivers.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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clk: stm32mp21: introduce STM32MP21 clock driver

As the STM32MP25 clock driver, this driver is based on the
clk-stm32-core API to manage STM32 gates, dividers, and multiplexer.

Signed-off-by: Yann

clk: stm32mp21: introduce STM32MP21 clock driver

As the STM32MP25 clock driver, this driver is based on the
clk-stm32-core API to manage STM32 gates, dividers, and multiplexer.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
becau

clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.

This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.

Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked

drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69

drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set

drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set correct ID
to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ack

drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES com

drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES command.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_sc

plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_scmi_clock_rates_by_step()" to be used by SCMI.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: configure STGEN flexgen in .enable ops

STGEN flexgen is skipped during RCC probe to prevent misalignment
between stgen_clk frequency and STGEN register. Configure the STGEN
flexgen i

clk: stm32mp25: configure STGEN flexgen in .enable ops

STGEN flexgen is skipped during RCC probe to prevent misalignment
between stgen_clk frequency and STGEN register. Configure the STGEN
flexgen in the .enable ops so that it is configured after the STGEN
itself is configured and started.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: fix clk_get_rate() when parent clock rate was changed

clk_get_rate() returns a cached value of the clock rate.

If the rate of the parent clock changed, then the rate is not
synchronized. Chan

clk: fix clk_get_rate() when parent clock rate was changed

clk_get_rate() returns a cached value of the clock rate.

If the rate of the parent clock changed, then the rate is not
synchronized. Change the function to compute all clock parents' rates
and return the synchronized value.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Fixes: 2305544b3b9b ("drivers: clk: add generic clock framework")

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drivers: clk: sam: rename the sama7g5 UTMI clocks for USB PHY

The UTMI clocks for USB PHY are handled in OP-TEE due to they are
controlled by the registers from RSTC (reset controller) which is
alwa

drivers: clk: sam: rename the sama7g5 UTMI clocks for USB PHY

The UTMI clocks for USB PHY are handled in OP-TEE due to they are
controlled by the registers from RSTC (reset controller) which is
always-secured.
SCMI "reset domain management protocol" makes it prossible to handle the
resets from the kernel running in normal world. So the code in kernel for
these clocks need to be enabled. Here renaming the clocks to avoid
registering them failed from the kernel.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: clk-stm32-core: fix use of ROUNDUP2_DIV() in stm32_div_get_rate()

Replace the use of ROUNDUP2_DIV() by ROUNDUP_DIV() in stm32_div_get_rate()
as some dividers may not be a power of two. In this

clk: clk-stm32-core: fix use of ROUNDUP2_DIV() in stm32_div_get_rate()

Replace the use of ROUNDUP2_DIV() by ROUNDUP_DIV() in stm32_div_get_rate()
as some dividers may not be a power of two. In this case, the platform
panics.

Fixes: 76d6685e5f3b ("tree-wide: use power-of-2 rounding macros where applicable")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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drivers: clk: sam: extend the time for waiting PLL ready

The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set

drivers: clk: sam: extend the time for waiting PLL ready

The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set a few
times with current timeout setting. Extend the time to make sure the check
is successful for any cases.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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tree-wide: use power-of-2 rounding macros where applicable

Use ROUNDUP2(), ROUNDUP2_OVERFLOW(), ROUNDUP2_DIV() and ROUNDDOWN2() at
places where the rounding argument is a variable value and we want

tree-wide: use power-of-2 rounding macros where applicable

Use ROUNDUP2(), ROUNDUP2_OVERFLOW(), ROUNDUP2_DIV() and ROUNDDOWN2() at
places where the rounding argument is a variable value and we want to
leverage the implementation of these routines optimized for a
power-of-2 rounding argument.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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clk: stm32mp25: add support for RIF configuration application

This driver now implements RIF configuration for RCC, which is a RIF
aware IP. It means that the RCC driver is in charge of configuring

clk: stm32mp25: add support for RIF configuration application

This driver now implements RIF configuration for RCC, which is a RIF
aware IP. It means that the RCC driver is in charge of configuring its
own RIF restrictions and that the RCC has dedicated RIF configuration
registers.

To avoid issues when manipulating clocks during OP-TEE boot or low-power
sequences, apply the RIF configuration for RCC resources at
driver_init_late level.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: change tree trace level

Change clock trace level of print tree so that
it can bee seen when it is requested by
xtest --stats --clocks.

Signed-off-by: Pascal Paillet <p.paillet@foss.st

drivers: clk: change tree trace level

Change clock trace level of print tree so that
it can bee seen when it is requested by
xtest --stats --clocks.

Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: shared_resource stops checking clock dependencies

Remove management of STM32MP15 secure clock support from the
platform specific share_resource.c driver. It is not needed STM32
ETZPC

plat-stm32mp1: shared_resource stops checking clock dependencies

Remove management of STM32MP15 secure clock support from the
platform specific share_resource.c driver. It is not needed STM32
ETZPC and RCC platform drivers now checks these dependencies.

Therefore the change removes stm32mp_register_clock_parents_secure()
and its related and ensures stm32mp_register_[non_]secure_xxx()
(from shared_resource.c driver) is not used for a clock (here PLL3).

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

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drivers: clk: stm32mp15: default disable mckprot hardening

Default disable RCC MCKPROT hardening configuration for STM32MP15
platforms since remoteproc driver enables it when required.

Remove disab

drivers: clk: stm32mp15: default disable mckprot hardening

Default disable RCC MCKPROT hardening configuration for STM32MP15
platforms since remoteproc driver enables it when required.

Remove disabling of RCC MCKPROT from STM32MP15 shared_resource driver
since this is now done from the STM32MP15 clock driver.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>

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