1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2018-2022, STMicroelectronics 4 */ 5 6 #ifndef __STM32_UTIL_H__ 7 #define __STM32_UTIL_H__ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/pinctrl.h> 12 #include <drivers/stm32_bsec.h> 13 #include <kernel/panic.h> 14 #include <stdint.h> 15 #include <tee_api_types.h> 16 #include <types_ext.h> 17 18 /* Backup registers and RAM utils */ 19 vaddr_t stm32mp_bkpreg(unsigned int idx); 20 21 /* Platform util for the RCC drivers */ 22 vaddr_t stm32_rcc_base(void); 23 24 /* Platform util for the GIC */ 25 vaddr_t get_gicd_base(void); 26 27 /* Platform util for PMIC support */ 28 bool stm32mp_with_pmic(void); 29 30 /* Power management service */ 31 #ifdef CFG_PSCI_ARM32 32 void stm32mp_register_online_cpu(void); 33 #else 34 static inline void stm32mp_register_online_cpu(void) 35 { 36 } 37 #endif 38 39 /* 40 * Generic spinlock function that bypass spinlock if MMU is disabled or 41 * lock is NULL. 42 */ 43 uint32_t may_spin_lock(unsigned int *lock); 44 void may_spin_unlock(unsigned int *lock, uint32_t exceptions); 45 46 /* Helper from platform RCC clock driver */ 47 struct clk *stm32mp_rcc_clock_id_to_clk(unsigned long clock_id); 48 49 #ifdef CFG_STM32MP1_SHARED_RESOURCES 50 /* Return true if @clock_id is shared by secure and non-secure worlds */ 51 bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 52 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 53 static inline bool stm32mp_nsec_can_access_clock(unsigned long clock_id 54 __unused) 55 { 56 return true; 57 } 58 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 59 60 extern const struct clk_ops stm32mp1_clk_ops; 61 62 #ifdef CFG_STM32MP1_SHARED_RESOURCES 63 /* Return true if and only if @reset_id relates to a non-secure peripheral */ 64 bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 65 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 66 static inline bool stm32mp_nsec_can_access_reset(unsigned int reset_id __unused) 67 { 68 return true; 69 } 70 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 71 72 /* Return rstctrl instance related to RCC reset controller DT binding ID */ 73 struct rstctrl *stm32mp_rcc_reset_id_to_rstctrl(unsigned int binding_id); 74 75 /* 76 * Structure and API function for BSEC driver to get some platform data. 77 * 78 * @base: BSEC interface registers physical base address 79 * @upper_start: Base ID for the BSEC upper words in the platform 80 * @max_id: Max value for BSEC word ID for the platform 81 */ 82 struct stm32_bsec_static_cfg { 83 paddr_t base; 84 unsigned int upper_start; 85 unsigned int max_id; 86 }; 87 88 void stm32mp_get_bsec_static_cfg(struct stm32_bsec_static_cfg *cfg); 89 90 /* 91 * Shared reference counter: increments by 2 on secure increment 92 * request, decrements by 2 on secure decrement request. Bit #0 93 * is set to 1 on non-secure increment request and reset to 0 on 94 * non-secure decrement request. These counters initialize to 95 * either 0, 1 or 2 upon their expect default state. 96 * Counters saturate to UINT_MAX / 2. 97 */ 98 #define SHREFCNT_NONSECURE_FLAG 0x1ul 99 #define SHREFCNT_SECURE_STEP 0x2ul 100 #define SHREFCNT_MAX (UINT_MAX / 2) 101 102 /* Return 1 if refcnt increments from 0, else return 0 */ 103 static inline int incr_shrefcnt(unsigned int *refcnt, bool secure) 104 { 105 int rc = !*refcnt; 106 107 if (secure) { 108 if (*refcnt < SHREFCNT_MAX) { 109 *refcnt += SHREFCNT_SECURE_STEP; 110 assert(*refcnt < SHREFCNT_MAX); 111 } 112 } else { 113 *refcnt |= SHREFCNT_NONSECURE_FLAG; 114 } 115 116 return rc; 117 } 118 119 /* Return 1 if refcnt decrements to 0, else return 0 */ 120 static inline int decr_shrefcnt(unsigned int *refcnt, bool secure) 121 { 122 int rc = 0; 123 124 if (secure) { 125 if (*refcnt < SHREFCNT_MAX) { 126 if (*refcnt < SHREFCNT_SECURE_STEP) 127 panic(); 128 129 *refcnt -= SHREFCNT_SECURE_STEP; 130 rc = !*refcnt; 131 } 132 } else { 133 rc = (*refcnt == SHREFCNT_NONSECURE_FLAG); 134 *refcnt &= ~SHREFCNT_NONSECURE_FLAG; 135 } 136 137 return rc; 138 } 139 140 static inline int incr_refcnt(unsigned int *refcnt) 141 { 142 return incr_shrefcnt(refcnt, true); 143 } 144 145 static inline int decr_refcnt(unsigned int *refcnt) 146 { 147 return decr_shrefcnt(refcnt, true); 148 } 149 150 /* 151 * Shared peripherals and resources registration 152 * 153 * Resources listed in enum stm32mp_shres assigned at run-time to the 154 * non-secure world, to the secure world or shared by both worlds. 155 * In the later case, there must exist a secure service in OP-TEE 156 * for the non-secure world to access the resource. 157 * 158 * Resources may be a peripheral, a bus, a clock or a memory. 159 * 160 * Shared resources driver API functions allows drivers to register the 161 * resource as secure, non-secure or shared and to get the resource 162 * assignation state. 163 */ 164 #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + i) 165 166 enum stm32mp_shres { 167 STM32MP1_SHRES_GPIOZ_0 = 0, 168 STM32MP1_SHRES_GPIOZ_1, 169 STM32MP1_SHRES_GPIOZ_2, 170 STM32MP1_SHRES_GPIOZ_3, 171 STM32MP1_SHRES_GPIOZ_4, 172 STM32MP1_SHRES_GPIOZ_5, 173 STM32MP1_SHRES_GPIOZ_6, 174 STM32MP1_SHRES_GPIOZ_7, 175 STM32MP1_SHRES_IWDG1, 176 STM32MP1_SHRES_USART1, 177 STM32MP1_SHRES_SPI6, 178 STM32MP1_SHRES_I2C4, 179 STM32MP1_SHRES_RNG1, 180 STM32MP1_SHRES_HASH1, 181 STM32MP1_SHRES_CRYP1, 182 STM32MP1_SHRES_I2C6, 183 STM32MP1_SHRES_RTC, 184 STM32MP1_SHRES_MCU, 185 STM32MP1_SHRES_PLL3, 186 STM32MP1_SHRES_MDMA, 187 STM32MP1_SHRES_SRAM1, 188 STM32MP1_SHRES_SRAM2, 189 STM32MP1_SHRES_SRAM3, 190 STM32MP1_SHRES_SRAM4, 191 192 STM32MP1_SHRES_COUNT 193 }; 194 195 bool stm32mp_allow_probe_shared_device(const void *fdt, int node); 196 197 #ifdef CFG_STM32MP1_SHARED_RESOURCES 198 /* Register resource @id as a secure peripheral */ 199 void stm32mp_register_secure_periph(enum stm32mp_shres id); 200 201 /* Register resource @id as a non-secure peripheral */ 202 void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 203 204 /* 205 * Register resource identified by @base as a secure peripheral 206 * @base: IOMEM physical base address of the resource 207 */ 208 void stm32mp_register_secure_periph_iomem(vaddr_t base); 209 210 /* 211 * Register resource identified by @base as a non-secure peripheral 212 * @base: IOMEM physical base address of the resource 213 */ 214 void stm32mp_register_non_secure_periph_iomem(vaddr_t base); 215 216 /* 217 * Register GPIO resource as a secure peripheral 218 * @bank: Bank of the target GPIO 219 * @pin: Bit position of the target GPIO in the bank 220 */ 221 void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 222 223 /* 224 * Register GPIO resource as a non-secure peripheral 225 * @bank: Bank of the target GPIO 226 * @pin: Bit position of the target GPIO in the bank 227 */ 228 void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 229 230 /* 231 * Register pin resource of a pin control state as a secure peripheral 232 * @bank: Bank of the target GPIO 233 * @pin: Bit position of the target GPIO in the bank 234 */ 235 void stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl); 236 237 /* 238 * Register pin resource of a pin control state as a non-secure peripheral 239 * @bank: Bank of the target GPIO 240 * @pin: Bit position of the target GPIO in the bank 241 */ 242 void stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl); 243 244 /* Return true if and only if resource @id is registered as secure */ 245 bool stm32mp_periph_is_secure(enum stm32mp_shres id); 246 247 /* Return true if and only if GPIO bank @bank is registered as secure */ 248 bool stm32mp_gpio_bank_is_secure(unsigned int bank); 249 250 /* Return true if and only if GPIO bank @bank is registered as non-secure */ 251 bool stm32mp_gpio_bank_is_non_secure(unsigned int bank); 252 253 /* Register number of pins in the GPIOZ bank */ 254 void stm32mp_register_gpioz_pin_count(size_t count); 255 256 #else /* CFG_STM32MP1_SHARED_RESOURCES */ 257 258 static inline void stm32mp_register_secure_periph(enum stm32mp_shres id 259 __unused) 260 { 261 } 262 263 static inline void stm32mp_register_non_secure_periph(enum stm32mp_shres id 264 __unused) 265 { 266 } 267 268 static inline void stm32mp_register_secure_periph_iomem(vaddr_t base __unused) 269 { 270 } 271 272 static inline void stm32mp_register_non_secure_periph_iomem(vaddr_t base 273 __unused) 274 { 275 } 276 277 static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 278 unsigned int pin __unused) 279 { 280 } 281 282 static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 283 unsigned int pin __unused) 284 { 285 } 286 287 static inline void 288 stm32mp_register_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 289 { 290 } 291 292 static inline void 293 stm32mp_register_non_secure_pinctrl(struct pinctrl_state *pinctrl __unused) 294 { 295 } 296 297 static inline bool stm32mp_periph_is_secure(enum stm32mp_shres id __unused) 298 { 299 return true; 300 } 301 302 static inline bool stm32mp_gpio_bank_is_secure(unsigned int bank __unused) 303 { 304 return true; 305 } 306 307 static inline bool stm32mp_gpio_bank_is_non_secure(unsigned int bank __unused) 308 { 309 return false; 310 } 311 312 static inline void stm32mp_register_gpioz_pin_count(size_t count __unused) 313 { 314 } 315 #endif /* CFG_STM32MP1_SHARED_RESOURCES */ 316 #endif /*__STM32_UTIL_H__*/ 317