drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked

drivers: clk: sam: select AUDIOPLL as the source for sama7g5 I2SMCC0 GCLK

Initialize the generic clock used by for sama7g5 I2SMCC0 peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69

drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set

drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers

When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set correct ID
to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ack

drivers: clk: sam: initialize the clocks used by sama7g5 PDMC0

Initialize the audio PLL and generic clocks used by for sama7g5 PDMC0
peripheral.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES com

drivers: clk: sam: initialize the clock range values for sama7g5 SCMI clocks

Initialize the clock range values for sama7g5 clocks so that they can be
used in responding SCMI CLOCK_DESCRIBE_RATES command.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_sc

plat-sam: add clock range support for the clocks used by SCMI

Add clock range attribute to the struct for the clocks.
New function for initializing the clock range for the clocks.
Implement "plat_scmi_clock_rates_by_step()" to be used by SCMI.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: rename the sama7g5 UTMI clocks for USB PHY

The UTMI clocks for USB PHY are handled in OP-TEE due to they are
controlled by the registers from RSTC (reset controller) which is
alwa

drivers: clk: sam: rename the sama7g5 UTMI clocks for USB PHY

The UTMI clocks for USB PHY are handled in OP-TEE due to they are
controlled by the registers from RSTC (reset controller) which is
always-secured.
SCMI "reset domain management protocol" makes it prossible to handle the
resets from the kernel running in normal world. So the code in kernel for
these clocks need to be enabled. Here renaming the clocks to avoid
registering them failed from the kernel.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: extend the time for waiting PLL ready

The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set

drivers: clk: sam: extend the time for waiting PLL ready

The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set a few
times with current timeout setting. Extend the time to make sure the check
is successful for any cases.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values.

drivers: clk: clk_get_rates_array() returns ordered rates

Explicitly state in clk_get_rates_array() inline description comment
that the output rates arrays is ordered by increasing frequency
values. This change allows to better fit the sole consumer of this
API function that is the SCMI server implementation. SCMI specification
states that discrete clock rates list shall follow this order.

Update at91_cpu_opp clock driver to ensure it satisfy this constraint.
The SAM platforms that embed this driver (sama7g5) already satisfy this
constraints but only at its DTS level. This change ensures the driver
will always.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: add the implement of CPU OPP clock

Register CPU OPP clock with the following operations:
- set_rate: call the operation of its parent
- get_rates_array: return the rates got fro

drivers: clk: sam: add the implement of CPU OPP clock

Register CPU OPP clock with the following operations:
- set_rate: call the operation of its parent
- get_rates_array: return the rates got from DT.
Skip CPU OPP clock register when OPP is not supported.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: prepare for CPU OPP (Operating Performance Points) support

Initialize clock rates array by parsing the device tree.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carr

plat-sam: prepare for CPU OPP (Operating Performance Points) support

Initialize clock rates array by parsing the device tree.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add definition for sama7g5 PMC_CPU_CKR register

The offset of "PMC CPU Clock Register" for sama7g5 is different from
the one for sama5d2.

Signed-off-by: Tony Han <tony.han@microc

drivers: clk: sam: add definition for sama7g5 PMC_CPU_CKR register

The offset of "PMC CPU Clock Register" for sama7g5 is different from
the one for sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: update the count of PCK clock for sama7g5

Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks
and for sama5d2 there're 4 PCK clocks.

Signed-off-by: Tony Han <ton

drivers: pm: sam: update the count of PCK clock for sama7g5

Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks
and for sama5d2 there're 4 PCK clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile

plat-sam: add support for Microchip sama7g54-ek board

Add the main functions for sama7g54 initialize, including:
- console_init()
- Matrix, TZC, TZPM, interrupt related
Update conf.mk and Makefile for sama7g5 OP-TEE support.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed

plat-sam: optimize the macro and makefile for building sama5d2 clocks

Rename 'CFG_DRIVERS_SAMA5D2_CLK' to 'CFG_SAMA5D2'.
Adjust the sequence of source files in 'core/drivers/clk/sam/sub.mk'.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ac

drivers: clk: sam: skip the NULL clocks when getting the clock by name

Skip the NULL items in the clock array when getting the clock by its name.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: add sama7g5 clock description

Define PLL, master, system, peripheral, generic clocks for sama7g5 and
register the clocks to clock provider.

Signed-off-by: Tony Han <tony.han@micr

drivers: clk: sam: add sama7g5 clock description

Define PLL, master, system, peripheral, generic clocks for sama7g5 and
register the clocks to clock provider.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.

drivers: clk: sam: add PLL clock driver for sama7g5

As PLL is compatible for sama7g5 and sam9x60, add sam9x60 PLL functions for
configuring sama7g5 PLL.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support generic clock for sama7g5

Add a mux table for select from different generic clock source.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Fori

drivers: clk: sam: update to support generic clock for sama7g5

Add a mux table for select from different generic clock source.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support main system bus clock for sama7g5

Add functions for configuring sama7g5 main system bus clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome

drivers: clk: sam: update to support main system bus clock for sama7g5

Add functions for configuring sama7g5 main system bus clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update to support slow clock for sama7g5

Add CLK_DT_DECLARE for sama7g5's slow clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissie

drivers: clk: sam: update to support slow clock for sama7g5

Add CLK_DT_DECLARE for sama7g5's slow clock.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add PMC definitions for sama7g5

Add PMC definitions to "at91_pmc.h" for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

drivers: clk: sam: add PMC definitions for sama7g5

Add PMC definitions to "at91_pmc.h" for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add UTMI clocks for sama7g5 USB PHY

Add functions for configuring UTMI clocks for sama7g5 USB PHY.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <je

drivers: clk: sam: add UTMI clocks for sama7g5 USB PHY

Add functions for configuring UTMI clocks for sama7g5 USB PHY.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: update UTMI clock for sama7g5

The frequency of the parent clock for UTMI is different with sama5d2.
The control of UTMI clock is different with sama5d2.

Signed-off-by: Tony Han <

drivers: clk: sam: update UTMI clock for sama7g5

The frequency of the parent clock for UTMI is different with sama5d2.
The control of UTMI clock is different with sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: dt_driver: swap TEE_result and retrieved device reference

Changes dt_driver callback function to return a TEE_Result value
and pass retrieved device reference by a output argument rather
than

core: dt_driver: swap TEE_result and retrieved device reference

Changes dt_driver callback function to return a TEE_Result value
and pass retrieved device reference by a output argument rather
than the opposite.

This change updates dt_driver.c, dt_driver.h and all drivers
implementing related dt_driver callback function.

As a consequence, this change removes all type definition related
to device specific callback handler function types which are useless
as all these now comply with type dt_driver_probe_func defined in
dt_driver.h.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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