core: riscv: include: add tee/entry_fast.h

This commit just copies entry_fast.h from ARM and renames
thread_smc_args to thread_abi_args.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>

core: riscv: include: add tee/entry_fast.h

This commit just copies entry_fast.h from ARM and renames
thread_smc_args to thread_abi_args.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S

This commits moves the following functions from thread_rv.S to a separate
file thread_optee_abi_rv.S:

- thread_return_fr

core: riscv: move TEE ABI handlers from thread_rv.S to thread_optee_abi_rv.S

This commits moves the following functions from thread_rv.S to a separate
file thread_optee_abi_rv.S:

- thread_return_from_nsec_call()
- thread_std_smc_entry() -> renamed to thread_std_abi_entry()
- thread_rpc()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure

SMC is an ARM-related keyword, make use thread_std_abi_entry instead of
thread_std_smc_entry.

Signed-off-by: Marouene Bouba

core: riscv: thread_arch.c: Use of ABI structure instead of SMC structure

SMC is an ARM-related keyword, make use thread_std_abi_entry instead of
thread_std_smc_entry.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_private_arch.h: add std and fast calls prototypes

This commit adds the following prototypes to thread_private_arch.h:
- thread_std_abi_entry()
- __thread_std_abi_entry()
- thread

core: riscv: thread_private_arch.h: add std and fast calls prototypes

This commit adds the following prototypes to thread_private_arch.h:
- thread_std_abi_entry()
- __thread_std_abi_entry()
- thread_handle_fast_abi()
- thread_handle_std_abi()

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args

SMC is an ARM-related keyword referring to Secure Monitor Call.
This commit renames thread_smc_args to thread_abi_args in
thread

core: riscv: thread_arch.h: rename thread_smc_args to thread_abi_args

SMC is an ARM-related keyword referring to Secure Monitor Call.
This commit renames thread_smc_args to thread_abi_args in
thread_arch.h and keeps the same members to guarantee compatibility
with the existing secure and non-secure domain communication protocol.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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plat-k3: Default to 2 core per cluster only for AM65x

All other SoCs have 4 cores per cluster, which is the default, or
they only have one cluster in which case this value is unimportant.

Signed-of

plat-k3: Default to 2 core per cluster only for AM65x

All other SoCs have 4 cores per cluster, which is the default, or
they only have one cluster in which case this value is unimportant.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sp: fix raw binary format SP loader

Loading a compressed raw binary format SP fails when read_compressed()
in embedded_ts.c is trying to allocate memory using bb_alloc(), since
the bounce buff

core: sp: fix raw binary format SP loader

Loading a compressed raw binary format SP fails when read_compressed()
in embedded_ts.c is trying to allocate memory using bb_alloc(), since
the bounce buffer in this user_mode_ctx is uninitialized. For ELF format
SPs ldelf is taking care of this, let's add the necessary initialization
to the raw binary format loader too.

Fixes: ef44161f847b ("core: update ts_store API with user space buffer")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Er

zynqmp: remove redundant platform config code

The hardware description is identical in all the platforms, there is no
need for specific ultra96 code to define base addresses.

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: unconditionally support manifest DT with FF-A

When configured for FF-A (CFG_CORE_FFA=y) unconditionally support
receiving at manifest device tree. This also makes CFG_DT=y mandatory
with FF-A.

core: unconditionally support manifest DT with FF-A

When configured for FF-A (CFG_CORE_FFA=y) unconditionally support
receiving at manifest device tree. This also makes CFG_DT=y mandatory
with FF-A.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: always save manifest DT with CFG_CORE_SEL2_SPMC=y

With CFG_CORE_SEL2_SPMC=y the manifest device tree is passed via boot
info from the SPMC at S-EL2. This manifest can contain configuration
nee

core: always save manifest DT with CFG_CORE_SEL2_SPMC=y

With CFG_CORE_SEL2_SPMC=y the manifest device tree is passed via boot
info from the SPMC at S-EL2. This manifest can contain configuration
needed later during boot, so save it always regardless of
CFG_CORE_PHYS_RELOCATABLE.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: map manifest using MEM_AREA_MANIFEST_DT

Maps the manifest using MEM_AREA_MANIFEST_DT and unmap it at the end of
boot. The manifest DT has a life cycle similar to an external DT, except
that it

core: map manifest using MEM_AREA_MANIFEST_DT

Maps the manifest using MEM_AREA_MANIFEST_DT and unmap it at the end of
boot. The manifest DT has a life cycle similar to an external DT, except
that it's mapped read-only and always secure. It's not available once
exiting after the initial boot

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: rename tos_fw_config_dt to manifest_dt

Renames tos_fw_config_dt to manifest_dt as a preparation for coming
patches to let it represent all device tree manifests provided in an
FF-A configurati

core: rename tos_fw_config_dt to manifest_dt

Renames tos_fw_config_dt to manifest_dt as a preparation for coming
patches to let it represent all device tree manifests provided in an
FF-A configuration.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Leisen <leisen1@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm.h: Add MPIDR definition for aff3 field

Adds define MPIDR_AFF3_SHIFT and MPIDR_AFF3_MASK.
And extend MPIDR_AFFLVL_MASK to 64 bits to support
the 64-bit MPIDR_EL1 on aarch64.

Signed-off-by:

core: arm.h: Add MPIDR definition for aff3 field

Adds define MPIDR_AFF3_SHIFT and MPIDR_AFF3_MASK.
And extend MPIDR_AFFLVL_MASK to 64 bits to support
the 64-bit MPIDR_EL1 on aarch64.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: Add write_icc_sgi1r() and write_icc_asgi1r()

Adds the wrapper function write_icc_sgi1r() and write_icc_asgi1r()
to write ICC_SGI1R and ICC_ASGI1R to generate group 1 SGIs for
the secure

core: arm64: Add write_icc_sgi1r() and write_icc_asgi1r()

Adds the wrapper function write_icc_sgi1r() and write_icc_asgi1r()
to write ICC_SGI1R and ICC_ASGI1R to generate group 1 SGIs for
the secure and non-secure state CPU.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: add secure memory registers for imx8m platforms

Add SECMEM_BASE and SECMEM_SIZE values.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@lina

core: imx: add secure memory registers for imx8m platforms

Add SECMEM_BASE and SECMEM_SIZE values.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: Fix setting the destination of FFA_ERROR calls

Fixing multiple issues in the destination logic of FFA_ERROR messages.
ffa_handle_error extracted the destination FF-A ID from the lower 16

core: spmc: Fix setting the destination of FFA_ERROR calls

Fixing multiple issues in the destination logic of FFA_ERROR messages.
ffa_handle_error extracted the destination FF-A ID from the lower 16 bit
of W1. First of all this register should only be set at the NS virtual
FF-A instance. Secondly W1 was not set correctly when an error happened
in ffa_handle_sp_direct_req and ffa_handle_sp_direct_resp. This could
cause sending FFA_ERROR messages to the wrong FF-A endpoint. The patch
clears up the faulty destination handling across all these functions.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: Clear reserved registers in FFA_ERROR calls

Clear reserved registers in FFA_ERROR calls which are declared MBZ in
the FF-A specification. This also prevents potential information leaks.

core: spmc: Clear reserved registers in FFA_ERROR calls

Clear reserved registers in FFA_ERROR calls which are declared MBZ in
the FF-A specification. This also prevents potential information leaks.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: spmc: Set initial SP state to busy

Set initial SP state to busy in order to prevent sending messages to
uninitialized SPs.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander

core: spmc: Set initial SP state to busy

Set initial SP state to busy in order to prevent sending messages to
uninitialized SPs.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64: write_64bit_pair()

Implement write_64bit_pair that write two 64 bits data together.

Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linar

core: arm64: write_64bit_pair()

Implement write_64bit_pair that write two 64 bits data together.

Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: update ts_store API with user space buffer

Updates the read() function pointer in struct ts_store_ops to take an
user space buffer in addition to the previous core buffer. Core buffers
are nor

core: update ts_store API with user space buffer

Updates the read() function pointer in struct ts_store_ops to take an
user space buffer in addition to the previous core buffer. Core buffers
are normal secure memory while user space buffers should only be accessed
using the user_access.h functions.

The different TA storage implementations are updated accordingly.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Add definitions of CLINT for platform spike

Add definitions for base address of CLINT, otherwise build failure
occurs for platform spike.

Signed-off-by: Alvin Chang <alvinga@andestech.

core: riscv: Add definitions of CLINT for platform spike

Add definitions for base address of CLINT, otherwise build failure
occurs for platform spike.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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arm: aspeed: Update secure memory layout

Update the TZDRAM region based on the 1GB DRAM space of
Aspeed AST2600/AST2700 EVBs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Je

arm: aspeed: Update secure memory layout

Update the TZDRAM region based on the 1GB DRAM space of
Aspeed AST2600/AST2700 EVBs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
inclu

riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
include path of RISC-V PLIC driver header is fixed.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Load register TP from thread_user_mode_rec in trap handler

RISC-V kernel uses TP register to store thread_core_local structure.
When the thread enters user mode, the value of TP is used

core: riscv: Load register TP from thread_user_mode_rec in trap handler

RISC-V kernel uses TP register to store thread_core_local structure.
When the thread enters user mode, the value of TP is used by user mode.
Therefore, when CPU enters trap handler, it needs to restore TP to get
thread_core_local structure. In previous implementation, the value of TP
is saved under kernel SP before entering user mode, and the trap handler
restores TP from that stack location. However, the value of TP has
already been saved into the thread_user_mode_rec structure, which is
also upon kernel SP, before entering user mode. So the value of TP can
be restored just from thread_user_mode_rec, instead of saving into
another location which is under the kernel SP.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: Support Privileged Access Never by CSR status.SUM bit

The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When

core: riscv: Support Privileged Access Never by CSR status.SUM bit

The SUM (Supervisor User Memory access) bit modifies the privilege with
which S-mode loads and stores the user virtual memory. When SUM bit is
0, S-mode accesses to pages whose U bit of corresponding PTE is set will
fault. When SUM bit is 1, these accesses are permitted.

When CFG_PAN is disabled in RISC-V architecture, the status.SUM bit is
initialized as 1 by default. Therefore all accesses to user pages will
succeed. When CFG_PAN is enabled, the status.SUM bit is initialized as
0, and only set to 1 when kernel needs to access user pages.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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