dts: stm32mp15: harden RCC secure configuration on ST boards

Enable STM32MP15 RCC secure hardening configuration on ST boards
(DK1, DK2, ED1 and EV1) to assign SoC clocks, reset controllers
and PWR

dts: stm32mp15: harden RCC secure configuration on ST boards

Enable STM32MP15 RCC secure hardening configuration on ST boards
(DK1, DK2, ED1 and EV1) to assign SoC clocks, reset controllers
and PWR regulators to OP-TEE secure world.

This change removes setting of &rcc node status property from
stm32mp157a-dk1.dts, stm32mp157c-dk2.dts as the property is
set from stm32mp15xx-dkx.dtsi that is included from the 2 former
DTS files.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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arm: aspeed: Add cflags for AST2600 SoCs

AST2600 only supports VFPv3-D16, which should be speicifed by cflags
to prevent undef-abort due to unsupoorted instructions generated by
compilers.

Signed-o

arm: aspeed: Add cflags for AST2600 SoCs

AST2600 only supports VFPv3-D16, which should be speicifed by cflags
to prevent undef-abort due to unsupoorted instructions generated by
compilers.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Neal Liu <neal_liu@aspeedtech.com>

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plat-stm32mp1: fix warning trace on TZC configuration check

Fix build warning reported by recent toolchains when TZDRAM
memory ends at the UINT32_MAX. This happends for example when
building for the

plat-stm32mp1: fix warning trace on TZC configuration check

Fix build warning reported by recent toolchains when TZDRAM
memory ends at the UINT32_MAX. This happends for example when
building for the stm32mp1-157C_EV1 platform. In such case was GCC
to emit the following warning trace:

core/arch/arm/plat-stm32mp1/plat_tzc400.c: In function ‘init_stm32mp1_tzc’:
core/arch/arm/plat-stm32mp1/plat_tzc400.c:107:61: warning: conversion from ‘uint64_t’ {aka ‘long long unsigned int’} to ‘vaddr_t’ {aka ‘long unsigned int’} changes value from ‘4294967296’ to ‘0’ [-Woverflow]
107 | if (!tzc_region_is_non_secure(region_index, tzdram_end,
| ^~~~~~~~~~

Fixes: 59c253f92c6c ("plat-stm32mp1: check TZC400 configuration")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: implement HiSilicon Queue Management (QM) module

The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management

drivers: implement HiSilicon Queue Management (QM) module

The Hisilicon QM is a Queue Management module.
In order to unify the interface between accelerator and software,
a unified queue management module QM is used to interact with software.
Each accelerator module integrates a QM. Software issues tasks to the SQ
(Submmision Queue),and the QM obtains the address of the SQE (Submmision
Queue Element). The BD (Buffer Description, same as SQE) information is
sent to the accelerator. After the task processing is complete, the
accelerator applies for a write-back address from the QM to write back
the SQ.

Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: scmi_server: expose IOD regulators

Replace stubs with recently introduced IO domain regulators
in SCMI server for STM32MP13 variants.

Acked-by: Patrick Delaunay <patrick.delaunay@fos

plat-stm32mp1: scmi_server: expose IOD regulators

Replace stubs with recently introduced IO domain regulators
in SCMI server for STM32MP13 variants.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: scmi_server: simplify regulators identification

Explicitly use a name ID of PMIC regulators identification and a
numerical ID for PWR and stubbed regulators identification while
there

plat-stm32mp1: scmi_server: simplify regulators identification

Explicitly use a name ID of PMIC regulators identification and a
numerical ID for PWR and stubbed regulators identification while
there is only 1 VREFBUF regulator that doesn't need such ID.

Remove string comparison from name to ID conversion for PWR in order
to simplify later use of SDMMC IO domain regulators on STM32MP13
variants.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32mp13: IO domain regulators

Define STM32MP13 IO domains regulators of the stm32mp13f-dk board
based on recently merge stm32mp1_regulator_io driver.

Acked-by: Patrick Delaunay <patrick.dela

dts: stm32mp13: IO domain regulators

Define STM32MP13 IO domains regulators of the stm32mp13f-dk board
based on recently merge stm32mp1_regulator_io driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: regulator: IO domain regulators for STM32MP13

Add STM32MP13 IO domains regulators allowing a consumer to
manage IO domains are voltage regulators.

Acked-by: Patrick Delaunay <patrick.delau

drivers: regulator: IO domain regulators for STM32MP13

Add STM32MP13 IO domains regulators allowing a consumer to
manage IO domains are voltage regulators.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: use IO_READ32_POLL_TIMEOUT()

Update stm32mp1_pwr driver to use IO_READ32_POLL_TIMEOUT() macro.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevall

plat-stm32mp1: pwr: use IO_READ32_POLL_TIMEOUT()

Update stm32mp1_pwr driver to use IO_READ32_POLL_TIMEOUT() macro.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: remove test on CFG_DRIVERS_REGULATOR

Remove tests on CFG_DRIVERS_REGULATOR value has the config switch
is always enabled on stm32mp1 platform.

Acked-by: Patrick Delaunay <patric

plat-stm32mp1: pwr: remove test on CFG_DRIVERS_REGULATOR

Remove tests on CFG_DRIVERS_REGULATOR value has the config switch
is always enabled on stm32mp1 platform.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
AP

plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
API functions. This configuration must be appleid at boot time and
when resuming from a system low power state.

This configuration depends on VDD voltage level. It can protected by
a OTP bit (HW2 bit 13) described in the chip reference manual for when
VDD is supplied with a voltage below 2.5V. As stated in the chip
reference manual, enabling HSLV mode with a VDD voltage level above
2.7V may be destructive hence the driver panics in such case.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: HLSV mode for IO domains

Add platform API functions stm32mp_set_hslv_state() and
stm32mp_enable_fixed_vdd_hslv() to configure High Speed Low Voltage
mode of IO domains.

Platf

plat-stm32mp1: syscfg: HLSV mode for IO domains

Add platform API functions stm32mp_set_hslv_state() and
stm32mp_enable_fixed_vdd_hslv() to configure High Speed Low Voltage
mode of IO domains.

Platform function stm32mp_enable_fixed_vdd_hslv() is designed for
fixed voltage IO domains that need to be enable at boot time only
since the supply voltage level never changes.

On STM32MP13 variants, SDMMC IO domains may not be supplied by fixed
voltage VDD but rather by a supply which voltage level can change
at runtime for example to support SD/MMC normative 1.8V and 3.3V voltage
modes. Therefore these IO domains require a runtime configuration
function implemented by stm32mp_set_hslv_state().

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: STM32MP13 dynamic IO compensation

Replace IO compensation API functions
stm32mp_syscfg_enable_io_compensation() and
stm32mp_syscfg_disable_io_compensation() with a new API fun

plat-stm32mp1: syscfg: STM32MP13 dynamic IO compensation

Replace IO compensation API functions
stm32mp_syscfg_enable_io_compensation() and
stm32mp_syscfg_disable_io_compensation() with a new API function
stm32mp_set_io_comp_by_index() dedicated to runtime configuration
of STM32MP13 SDMMC's domains IO compensation only.

On STM32MP15 variant, the configuration is enabled only during
initialization. On STM32MP13 variant, the same feature is also enabled
during initialization but the device embeds 2 more IO domains
(SDMMC1 and SDMMC2) for which the new API function allow runtime
reconfiguration support.

For sake of simplicity, keep related clocks always on.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: compute base address once

Compute SYSCFG virtual address only once.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@f

plat-stm32mp1: syscfg: compute base address once

Compute SYSCFG virtual address only once.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: syscfg: use U() macro

Use U() macro where applicable in stm32mp1_syscfg.c driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.cheval

plat-stm32mp1: syscfg: use U() macro

Use U() macro where applicable in stm32mp1_syscfg.c driver.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: interrupt: registering interrupt providers

Adds interrupt chip framework API functions for an interrupt controller
to register as an interrupt provider in the driver probing sequence
based on

core: interrupt: registering interrupt providers

Adds interrupt chip framework API functions for an interrupt controller
to register as an interrupt provider in the driver probing sequence
based on device tree. This allows interrupt consumer to be deferred
when a dependent interrupt controller is not yet initialized.

Interrupt controllers register a driver in DT_DRIVER providers list
with: interrupt_register_provider().

Interrupt consumer can get their interrupt through DT data with
interrupt_dt_get(), interrupt_dt_get_by_index() or
interrupt_dt_get_by_name().

This change removes inclusion of interrupt.h from kernel/dt.h as it is
not needed and conflicts with inclusion of kernel/dt.h from
kernel/interrupt.h.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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tree-wide: remove useless newline character in *MSG() messages

The *MSG() macros take care of printing a newline. Adding a newline
character ('\n') is useless. Remove it.

Signed-off-by: Vincent Mai

tree-wide: remove useless newline character in *MSG() messages

The *MSG() macros take care of printing a newline. Adding a newline
character ('\n') is useless. Remove it.

Signed-off-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: fixup of transfer list entry overriding

Expand the data size of DTB transfer list entry to the max allocable
size to reserve sufficient space for new nodes.
This fixes a potential issue t

core: arm: fixup of transfer list entry overriding

Expand the data size of DTB transfer list entry to the max allocable
size to reserve sufficient space for new nodes.
This fixes a potential issue that the amended DTB transfer entry
overrides other entries followed by, when inserting new nodes.

When CFG_TRANSFER_LIST is enabled, instead of CFG_DTB_MAX_SIZE,
the DTB max size will be given by a calculation of the remaining space
in the transfer list mapped memory.

Fixes: 66763721fe35 ("core: add support for transfer list")
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add new argument to init_external_dt()

Add argument to function init_external_dt() to allow callers to specify
the maximum size of external DTB to be initialized.

Signed-off-by: Raymond Mao <

core: add new argument to init_external_dt()

Add argument to function init_external_dt() to allow callers to specify
the maximum size of external DTB to be initialized.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: relax CFG_ASAN_SHADOW_OFFSET configuration value

Fixes CFG_ASAN_SHADOW_OFFSET configuration value for vexpress
platform qemu* flavors. Before this change CFG_ASAN_SHADOW_OFFSET
variab

plat-vexpress: relax CFG_ASAN_SHADOW_OFFSET configuration value

Fixes CFG_ASAN_SHADOW_OFFSET configuration value for vexpress
platform qemu* flavors. Before this change CFG_ASAN_SHADOW_OFFSET
variable needed a specific scope to override the default value set
by platform conf.mk file.

Fixes: 24475b562b81 ("plat-vexpress: move CFG_TEE_CORE_NB_CORE to platform conf.mk")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: relax CFG_TEE_CORE_NB_CORE configuration value

Fixes CFG_TEE_CORE_NB_CORE configuration value for all vexpress
platform flavors. Before this change CFG_TEE_CORE_NB_CORE variable
neede

plat-vexpress: relax CFG_TEE_CORE_NB_CORE configuration value

Fixes CFG_TEE_CORE_NB_CORE configuration value for all vexpress
platform flavors. Before this change CFG_TEE_CORE_NB_CORE variable
needed a specific scope to override the default value set by platform
conf.mk file.

Fixes: 24475b562b81 ("plat-vexpress: move CFG_TEE_CORE_NB_CORE to platform conf.mk")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: fix order for CFG_REGULATOR_FIXED

Changes CFG_REGULATOR_FIXED config setting location to match alphabetical
order.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
S

plat-stm32mp1: conf: fix order for CFG_REGULATOR_FIXED

Changes CFG_REGULATOR_FIXED config setting location to match alphabetical
order.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: enable support for GPIO regulators

Enables support for GPIO regulators on platform stm32mp1 when
CFG_STM32_GPIO is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.

plat-stm32mp1: conf: enable support for GPIO regulators

Enables support for GPIO regulators on platform stm32mp1 when
CFG_STM32_GPIO is enabled.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: allow CFG_TZSRAM_START being defined when pager is disabled

Fixes case when a platform configuration defines CFG_TZSRAM_START but
does not use the pager. CFG_TZSRAM_START defines the base

core: arm: allow CFG_TZSRAM_START being defined when pager is disabled

Fixes case when a platform configuration defines CFG_TZSRAM_START but
does not use the pager. CFG_TZSRAM_START defines the based address
of the memory used for resident memory and page pool when CFG_WITH_PAGER
is enabled.

Since below mentioned commit, TZSRAM_BASE being defined makes core_mmu.c
to assume there are 2 secure memories for OP-TEE core internal use. This
change ensures that when CFG_WITH_PAGER is disabled, TZSRAM is not
defined even if the platform configuration sets CFG_TZSRAM_START.

An example of such issues is when testing an STM32MP15 variant of
platform stm32mp1 with pager being disabled. Before this change,
OP-TEE boot sequence fails with a error trace message like:
E/TC:0 0 Panic 'Unexpected TZC configuration on secure region' at core/arch/arm/plat-stm32mp1/plat_tzc400.c:102 <init_stm32mp1_tzc>

Indeed debug trace messages can show that an invalid physical memory
area has been registered by core as TEE_RAM_RO, as shown below. Note that
for that platform, internal secure SYSRAM range is [0x2ffc000 0x30000000]:
D/TC:0 add_phys_mem:667 ram_start type TEE_RAM_RO 0x2ffc0000 size 0xae040000

Fixes: e09739a8a6a1 ("core: core_mmu.c: use secure_only[] where possible")
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: scmi_server: report invalid regulator state request

Changes the SCMI return code from SCMI_GENERIC_ERROR to
SCMI_INVALID_PARAMETERS when the requested state is not one of
the 2 suppor

plat-stm32mp1: scmi_server: report invalid regulator state request

Changes the SCMI return code from SCMI_GENERIC_ERROR to
SCMI_INVALID_PARAMETERS when the requested state is not one of
the 2 supported SCMI voltage domain states
(SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_ON or
SCMI_VOLTAGE_DOMAIN_CONFIG_ARCH_OFF).

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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