plat-stm32mp1: enable support for fixed regulators

Enables support for fixed regulators on platform stm32mp1.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carr

plat-stm32mp1: enable support for fixed regulators

Enables support for fixed regulators on platform stm32mp1.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove unused mobj_mm_alloc()

Removes the now unused mobj_mm_alloc(), struct mobj_mm, and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienn

core: remove unused mobj_mm_alloc()

Removes the now unused mobj_mm_alloc(), struct mobj_mm, and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: remove unused mobj_seccpy_shm_alloc()

Removes the now unused mobj_seccpy_shm_alloc(), struct mobj_seccpy_shm,
and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by:

core: remove unused mobj_seccpy_shm_alloc()

Removes the now unused mobj_seccpy_shm_alloc(), struct mobj_seccpy_shm,
and friends.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Fix logic of thread_{get/set}_exceptions()

In ARM, the bits in DAIF register are used to mask the interrupts. While
in RISC-V, the bits in CSR XIE are used to enable(unmask) correspondi

core: riscv: Fix logic of thread_{get/set}_exceptions()

In ARM, the bits in DAIF register are used to mask the interrupts. While
in RISC-V, the bits in CSR XIE are used to enable(unmask) corresponding
interrupt sources.

To not modify the function of thread_get_exceptions(), we invert the
bits after reading the value of CSR XIE, as mask.

To not modify the function of thread_set_exceptions(), we invert the
bits in given "exceptions" before writing "exceptions" into CSR
XIE. Therefore, the intended masked exception bits will be cleared
when we write the final value into CSR XIE to mask those interrupts.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Register thread_vector_table in primary CPU initialization

When primary CPU has initialized everything, it registers the address
of thread_vector_table into higher privileged software v

core: riscv: Register thread_vector_table in primary CPU initialization

When primary CPU has initialized everything, it registers the address
of thread_vector_table into higher privileged software via a1 register.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Implement thread_vector_table for ABI and FIQ entries

Implement thread_vector_table which only includes entries for standard
ABI, fast ABI, and foreign interrupts. Most of code is refer

core: riscv: Implement thread_vector_table for ABI and FIQ entries

Implement thread_vector_table which only includes entries for standard
ABI, fast ABI, and foreign interrupts. Most of code is referenced from
ARM architecture. The thread_vector_table will be registered into higher
privileged software, such as M-mode firmware. The higher privileged
software can jump(mret) to OP-TEE based on this vector table.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Implement SBI based protocol

Rename thread_return_from_nsec_call() to thread_return_to_ree() for more
general behavior, since TEE might not only be called by REE, but also
do something

core: riscv: Implement SBI based protocol

Rename thread_return_from_nsec_call() to thread_return_to_ree() for more
general behavior, since TEE might not only be called by REE, but also
do something on its own initiative (e.g., handle secure interrupts).

This commit also implements SBI based protocol used to return control to
REE. The register a7 encodes SBI TEE extension ID, which is temporarily
defined here. We may have ratified SBI TEE extension in the future and
we can apply ratified ID at that time. The register a6 is unused and
encoded as 0. The returned arguments are encoded into registers a0~a5
and should be provided by the caller.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Implement panic_at_abi_return as guard of ABI call

The ABI call to REE domain should not return. We implement
panic_at_abi_return macro as guard of ABI call. When the ABI call return
il

core: riscv: Implement panic_at_abi_return as guard of ABI call

The ABI call to REE domain should not return. We implement
panic_at_abi_return macro as guard of ABI call. When the ABI call return
illegally, the system will enter panic or an infinite loop.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ffa: use FFA_NORMAL_WORLD_RESUME

Prior to this FFA_INTERRUPT was always completed using FFA_MSG_WAIT,
but at S-EL1 FFA_NORMAL_WORLD_RESUME should be used instead. So fix this
by completing a s

core: ffa: use FFA_NORMAL_WORLD_RESUME

Prior to this FFA_INTERRUPT was always completed using FFA_MSG_WAIT,
but at S-EL1 FFA_NORMAL_WORLD_RESUME should be used instead. So fix this
by completing a secure interrupt that has preempted the normal world with
FFA_NORMAL_WORLD_RESUME if configured with SPMC at S-EL1.

Fixes: 67fec989b586 ("core: ffa: correct response to FFA_INTERRUPT")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Balint Dobszay <balint.dobszay@arm.com>

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core: sp: fix FFA_MEM_RECLAIM checks

Currently it is assumed that a NS endpoint's ID is always 0. This is not
true if multiple VMs are present in the NWd, so the check will fail when
reclaiming shar

core: sp: fix FFA_MEM_RECLAIM checks

Currently it is assumed that a NS endpoint's ID is always 0. This is not
true if multiple VMs are present in the NWd, so the check will fail when
reclaiming shared memory from an SP. Fix this by removing the owner ID
check if the reclaim call comes from NWd, in this case the necessary
checks are done by the hypervisor.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: optee_ffa.h: fix a spell error in ABI description

Fixes a spell error in the comment describing OPTEE_FFA_UNREGISTER_SHM ABI.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-b

core: optee_ffa.h: fix a spell error in ABI description

Fixes a spell error in the comment describing OPTEE_FFA_UNREGISTER_SHM ABI.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: return an error on unknown blocking calls

Until now we have panicked on unknown blocking calls. The caller can't
recover from that so return an error instead.

Signed-off-by: Jens Wikland

core: ffa: return an error on unknown blocking calls

Until now we have panicked on unknown blocking calls. The caller can't
recover from that so return an error instead.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: fix race in mobj_put() and ffa_inactivate()

Prior to this patch there was a race condition when mobj_put()
is calling ffa_inactivate().
D/TC:0 0 ffa_inactivate:525 cookie 0x100000000000
D

core: ffa: fix race in mobj_put() and ffa_inactivate()

Prior to this patch there was a race condition when mobj_put()
is calling ffa_inactivate().
D/TC:0 0 ffa_inactivate:525 cookie 0x100000000000
D/TC:0 1 mobj_ffa_get_by_cookie:401 cookie 0x100000000000 active: refc 1
D/TC:? 1 read_console:114 got 0xd
D/TC:0 1 ffa_inactivate:525 cookie 0x100000000000
D/TC:0 0 ffa_inactivate:525 cookie 0x100000000000
E/TC:0 0 Panic at core/arch/arm/mm/mobj_ffa.c:527 <ffa_inactivate>
E/TC:0 0 TEE load address @ 0xe100000
E/TC:0 0 Call stack:
E/TC:0 0 0x0e108c0c print_kernel_stack at ??:?
E/TC:0 0 0x0e115b8c __do_panic at core/kernel/panic.c:24
E/TC:0 0 0x0e10a238 ffa_inactivate at mobj_ffa.c:?
E/TC:0 0 0x0e107318 __thread_std_smc_entry at ??:?

As now explained in ffa_inactivate():
/*
* pop_from_list() can fail to find the mobj if we had just
* decreased the refcount to 0 in mobj_put() and was going to
* acquire the shm_lock but another thread found this mobj and
* reinitialized the refcount to 1. Then before we got cpu time the
* other thread called mobj_put() and deactivated the mobj again.
* ...
*/

If our thread is delayed even further we may even inactivate an
unrelated mobj that happened to reuse the same piece of memory.

Fix this by adding another guarding condition so that the mobj is
guaranteed to be valid until ffa_inactivate() has returned. By adding a
new member in struct mobj_ffa, inactive_refs, we keep track of
references even when the mobj have been moved to the inactive list.

Adds a comment describing the non-trivial life cycle of struct mobj_ffa.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: fix the DDR configuration of the mx8dxl

Add base address and size of the second DDR size.
Set the physical address size to 40 bits instead of 32 bits. This is
required for platforms with

core: imx: fix the DDR configuration of the mx8dxl

Add base address and size of the second DDR size.
Set the physical address size to 40 bits instead of 32 bits. This is
required for platforms with more and 4G of DDR.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: allow CAAM driver compilation on mx8dxl

Allow the compilation of the CAAM driver for mx8dxl platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <je

core: imx: allow CAAM driver compilation on mx8dxl

Allow the compilation of the CAAM driver for mx8dxl platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: stm32mp1_pmic: register to DT_DRIVER

Initialize stm32mp1_pmic device driver from DT_DRIVER instead of
fixed initcall level. This change requires stm32_i2c bus driver
to also be probed

plat-stm32mp1: stm32mp1_pmic: register to DT_DRIVER

Initialize stm32mp1_pmic device driver from DT_DRIVER instead of
fixed initcall level. This change requires stm32_i2c bus driver
to also be probed from the DT_DRIVER framework.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: stm32mp1_pmic: allocate I2C handle

Allocates I2C handle in stm32mp1_pmic driver. This changes prepares
at later change replacing initcall initialization for dt_driver probing
initiali

plat-stm32mp1: stm32mp1_pmic: allocate I2C handle

Allocates I2C handle in stm32mp1_pmic driver. This changes prepares
at later change replacing initcall initialization for dt_driver probing
initialization.

By the way, remove unused variables and reorder included header files.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: stm32mp1_pmic: save DT status once for all

Saves PMIC DT node status during initialization. This changes prepares
at later change replacing initcall initialization for dt_driver probi

plat-stm32mp1: stm32mp1_pmic: save DT status once for all

Saves PMIC DT node status during initialization. This changes prepares
at later change replacing initcall initialization for dt_driver probing
initialization.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: stm32mp1_pmic: remove unused stm32mp_dt_pmic_status()

Removes unused function stm32mp_dt_pmic_status().

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas B

plat-stm32mp1: stm32mp1_pmic: remove unused stm32mp_dt_pmic_status()

Removes unused function stm32mp_dt_pmic_status().

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: conf: default enable CFG_DRIVERS_I2C

Default enable I2C bus framework on platform stm32mp1.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <tho

plat-stm32mp1: conf: default enable CFG_DRIVERS_I2C

Default enable I2C bus framework on platform stm32mp1.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: shared_resources: simplify GPIOZ bank pin count

Changes initialization of GPIOZ bank pin count from the DT bank
node now using the GPIO bank driver probing to get and save the
informa

plat-stm32mp1: shared_resources: simplify GPIOZ bank pin count

Changes initialization of GPIOZ bank pin count from the DT bank
node now using the GPIO bank driver probing to get and save the
information rather than service_init() initcall level as prior
this change.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-k3: drivers: Open TRNG firewall for TIFS

On devices with PLATFORM=k3-am62x, there is only one SA2UL instance,
which is being shared between TIFS and OP-TEE.

Blocking access to TRNG from all ot

plat-k3: drivers: Open TRNG firewall for TIFS

On devices with PLATFORM=k3-am62x, there is only one SA2UL instance,
which is being shared between TIFS and OP-TEE.

Blocking access to TRNG from all other entities other than OP-TEE
is causing firewall exception when being accessed by TIFS.

While there are other platforms with only one sa2ul instance, on AM62x
we support low power mode, in which TIFS access TRNG while waking up
from deep sleep. On other devices, use of TRNG by TIFS is limited to
the time till OP-TEE initializes and firewalls it for other entities.

Allow access to TIFS to use SA2UL TRNG along with OP-TEE.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>

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plat-k3: drivers: Fix values for FW_SECURE_ONLY and FW_NON_SECURE

Fix values for permission bits for secure user, secure supervisor,
non-secure user and non-secure supervisor.

0th-7th bits are for

plat-k3: drivers: Fix values for FW_SECURE_ONLY and FW_NON_SECURE

Fix values for permission bits for secure user, secure supervisor,
non-secure user and non-secure supervisor.

0th-7th bits are for secure user/supervisor permissions and
8th-15th bits are for non-secure user/supervisor permission.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>

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core: arm: fix style issues in asm-defines.c

Fixing a few cases of alignment that doesn't match open parenthesis.

Fixes: c02f9fb09df2 ("arm: add auto generated asm-defines.h")
Signed-off-by: Jens W

core: arm: fix style issues in asm-defines.c

Fixing a few cases of alignment that doesn't match open parenthesis.

Fixes: c02f9fb09df2 ("arm: add auto generated asm-defines.h")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: preserve 64bit smccc when possible

Prior to this patch when a FFA_MSG_SEND_DIRECT_REQ_64 was received the
response was sent as FFA_MSG_SEND_DIRECT_RESP_32. While not breaking
with the FF-

core: ffa: preserve 64bit smccc when possible

Prior to this patch when a FFA_MSG_SEND_DIRECT_REQ_64 was received the
response was sent as FFA_MSG_SEND_DIRECT_RESP_32. While not breaking
with the FF-A specification, it's still a bit unexpected and will cause
an error in the FF-A framework driver. So fix this by keeping track of
the SMCCC (SMC Calling Convention) used during the current
FFA_MSG_SEND_DIRECT_REQ and respond with matching SMCCC.

This has no impact on AArch32 mode since only the 32-bit SMCCC is valid
in that case. The greatest impact on AArch64 is that we must be able to
find out the current SMCCC during RPC, this means storing it in struct
thread_core_local to be able to access it in assembly low level
routines.

Support for FFA_MSG_SEND_DIRECT_REQ_64 is also advertised in
FFA_FEATURES.

Fixes: 15da69cff2ca ("core: ffa: Enable handling 64-bit direct messages")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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