riscv: sbi: minor cleanup for SBI HSM related definitions

Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated
type for function ID definition for better clarity and consistency
with th

riscv: sbi: minor cleanup for SBI HSM related definitions

Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated
type for function ID definition for better clarity and consistency
with the following commits.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: at91: add device trees for sama7g54_ek

Add the header file for pin definitions.
Add dtsi & dts files for sama7g54_ek.

Signed-off-by: Tony Han <tony.han@microchip.com>
[TP: Update device trees

dts: at91: add device trees for sama7g54_ek

Add the header file for pin definitions.
Add dtsi & dts files for sama7g54_ek.

Signed-off-by: Tony Han <tony.han@microchip.com>
[TP: Update device trees for sama7g54_ek according kernel dtsi and
dts files for the sama7g54_ek.]
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: sama5d2: add huk node for the NVMEM hardware unique key

Add the definition of the NVMEM HUK controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acke

dts: sama5d2: add huk node for the NVMEM hardware unique key

Add the definition of the NVMEM HUK controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: sama5d2: add NVMEM die_id node

Add the definition of the NVMEM die id controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier

dts: sama5d2: add NVMEM die_id node

Add the definition of the NVMEM die id controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: enable NVMEM unique hardware key and die id support

Enable NVMEM support to allow reading hardware unique key from
the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Sign

plat-sam: enable NVMEM unique hardware key and die id support

Enable NVMEM support to allow reading hardware unique key from
the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://githu

core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://github.com/riscv-non-isa/riscv-semihosting

Add semihosting.S into RISC-V kernel folder to implement the trap
instruction sequence.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: implement plat_get_freq() for sama7g5

Sama7g5 platform does not have support for the ARM generic timer
extension, so plat_get_freq() needs to be updated to be able to
probe clocks early us

plat-sam: implement plat_get_freq() for sama7g5

Sama7g5 platform does not have support for the ARM generic timer
extension, so plat_get_freq() needs to be updated to be able to
probe clocks early using the device tree as for the sama5d2.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: register additional sama7g5 clocks for SCMI usage

- Add the macro definitions for each SCMI clock.
- Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Thomas Perrot <thomas

plat-sam: register additional sama7g5 clocks for SCMI usage

- Add the macro definitions for each SCMI clock.
- Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: register sama7g5 clocks for SCMI usage

Add the macro definitions for each SCMI clock.
Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ac

plat-sam: register sama7g5 clocks for SCMI usage

Add the macro definitions for each SCMI clock.
Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp2: add pm support on stm32mp25

Add support of low power mode on stm32mp25 and perform the needed OP-TEE
bookkeeping before PSCI executes a power management sequence, with the 3
hooks cal

plat-stm32mp2: add pm support on stm32mp25

Add support of low power mode on stm32mp25 and perform the needed OP-TEE
bookkeeping before PSCI executes a power management sequence, with the 3
hooks called by TF-A SPD :
- thread_system_off_handler()
- thread_cpu_resume_handler()
- thread_cpu_suspend_handler()

On PSCI system off request, the STPMIC25 driver need to configure the
regulators properly to handle the always on domain with the board
configuration (PMIC switch OFF, with coin cell, or standby DDR off).

For PSCI suspend requests, the STM32MP25 family supports 5 power levels
in the PSCI topology to handle the regulators configuration done in STPMIC2
for low poser modes, in particular to differentiate the tension for LP and
the LPLV modes:

power level (System mode for a0= Max power level powered down)
--------------------------------------------------------------------------
0: CPU1 core#0 or core#1 (Stop1 or LP-Stop1)
1: D1 domain (LPLV-Stop1)
2: LPLV D1 (Stop2 or LP-Stop2)
3: D2 (LPLV-Stop2)
4: LPLV D2 (Standby)
5: MAX (PowerOff: Standby or VBat)

The hook calls pm_change_state with generic HINT for inform STM32MP25
drivers to operation to performed on suspend/resume:
- PM_HINT_CLOCK_STATE
the IP clock will be deactivated, the pending operation should stop,
cleanup operation can be done on HW to prepare the clock freeze
(optional support by driver)
- PM_HINT_CONTEXT_STATE
called for System level standby when the IP configuration is lost.
The state of each device must be saved in RAM which is preserved
(DDR in self-refresh, mandatory)

Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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plat-sam: fix static shared memory address and size

Disable the dynamic shared memory allocation that isn't used on SAM
platforms, otherwise the following issue occurs, since the commit
8a6ca1480ddc

plat-sam: fix static shared memory address and size

Disable the dynamic shared memory allocation that isn't used on SAM
platforms, otherwise the following issue occurs, since the commit
8a6ca1480ddc ("core: arm: get DDR range from embedded DTB"):

I/TC: Embedded DTB found
E/TC:0 0 check_phys_mem_is_outside:409 Non-sec mem (0x20800000:0x1f800000) overlaps map (type 18 0x21400000:0x1000)
E/TC:0 0 Panic at core/mm/core_mmu.c:413 <check_phys_mem_is_outside>
E/TC:0 0 TEE load address @ 0x20000000
E/TC:0 0 Call stack:
E/TC:0 0 0x20005655 print_kernel_stack at core/arch/arm/kernel/unwind_arm32.c:109
E/TC:0 0 0x2001c52d __do_panic at core/kernel/panic.c:80
E/TC:0 0 0x200276c1 check_phys_mem_is_outside at core/mm/core_mmu.c:413
E/TC:0 0 0x2002780f core_mmu_set_discovered_nsec_ddr at core/mm/core_mmu.c:481
E/TC:0 0 0x200050b3 discover_nsec_memory at core/arch/arm/kernel/boot.c:1055
E/TC:0 0 0x20005247 boot_init_primary_late at core/arch/arm/kernel/boot.c:1210
E/TC:0 0 0x200001fc reset_primary at core/arch/arm/kernel/entry_a32.S:532

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-mediatek: add support for MT7988 SoC

Add OP-TEE support for the MT7988 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by:

plat-mediatek: add support for MT7988 SoC

Add OP-TEE support for the MT7988 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: kernel: add runtime check for CE

Add runtime check during boot for supported ARMv8 Crypto Extensions.
Core will panic if configuration enables an ARMv8 CE feature
that the hardware does n

core: arm: kernel: add runtime check for CE

Add runtime check during boot for supported ARMv8 Crypto Extensions.
Core will panic if configuration enables an ARMv8 CE feature
that the hardware does not support.

Link: https://github.com/OP-TEE/optee_os/issues/6631
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add helper functions for checking CE support

Add helper functions for checking implementation of SHA1, SHA256,
SHA512, SHA3, SM3, SM4 instructions.

Acked-by: Etienne Carriere <etienne.ca

core: arm: add helper functions for checking CE support

Add helper functions for checking implementation of SHA1, SHA256,
SHA512, SHA3, SM3, SM4 instructions.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add check in aarch32 for feat_crc32_implemented()

Add support for checking CRC32 HW instruction in aarch32.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wik

core: arm: add check in aarch32 for feat_crc32_implemented()

Add support for checking CRC32 HW instruction in aarch32.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm64: remove ID_AA64ISAR0_EL1 macros

Remove old definitions for ID_AA64ISAR0_EL1 CRC32 bitmask
and shift.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander

core: arm64: remove ID_AA64ISAR0_EL1 macros

Remove old definitions for ID_AA64ISAR0_EL1 CRC32 bitmask
and shift.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: rewrite feat_crc32_implemented()

Rewrite check in feat_crc32_implementedfor for ARM64.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklande

core: arm: rewrite feat_crc32_implemented()

Rewrite check in feat_crc32_implementedfor for ARM64.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm64: add masks for ID_AA64ISAR0_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_AA64ISAR0_EL1 register:

Algo Bits
SM4 - [43:40]
SM3 - [39:36]
SHA

core: arm64: add masks for ID_AA64ISAR0_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_AA64ISAR0_EL1 register:

Algo Bits
SM4 - [43:40]
SM3 - [39:36]
SHA3 - [35:32]
RDM - [31:28]
TME - [27:24]
Atomic - [23:20]
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [11:8]
AES - [7:4]

For additional details check ARM Architecture Reference Manual
for ARMv8-A architecture profile.
ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0.

Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: arm: add masks for ID_ISAR5_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_ISAR5_EL1 register:

Algo Bits
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [1

core: arm: add masks for ID_ISAR5_EL1 fields

Add masks for obtaining Crypto Extensions support status from
ID_ISAR5_EL1 register:

Algo Bits
CRC32 - [19:16]
SHA2 - [15:12]
SHA1 - [11:8]
AES - [7:4]

For additional details check ARM Architecture Reference Manual
for ARMv8-A architecture profile.
D10.2.66 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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core: virt, ffa: keep guest partition until resources are reclaimed

Move a struct guest_partition to prtn_destroy_list if there are
resources remaining to be reclaimed by the hypervisor. Currently t

core: virt, ffa: keep guest partition until resources are reclaimed

Move a struct guest_partition to prtn_destroy_list if there are
resources remaining to be reclaimed by the hypervisor. Currently this is
needed with FF-A and SPMC at S-EL1.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: store shm_bits in partition for SPMC at S-EL1

Store the bitmask keeping track of allocated shared memory handles in
the current partition when configured with CFG_NS_VIRTUALIZATION and
CF

core: ffa: store shm_bits in partition for SPMC at S-EL1

Store the bitmask keeping track of allocated shared memory handles in
the current partition when configured with CFG_NS_VIRTUALIZATION and
CFG_CORE_SEL1_SPMC.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: ffa: add SPMC_CORE_SEL1_MAX_SHM_COUNT

Add SPMC_CORE_SEL1_MAX_SHM_COUNT, telling how many shared memory object
are supported in a configuration with SPMC at S-EL1.

Signed-off-by: Jens Wiklande

core: ffa: add SPMC_CORE_SEL1_MAX_SHM_COUNT

Add SPMC_CORE_SEL1_MAX_SHM_COUNT, telling how many shared memory object
are supported in a configuration with SPMC at S-EL1.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: thread_spmc.c: add set_simple_ret_val()

Simplify common FFA_ERRROR/FFA_SUCCESS_32 patterns where an error code
is returned on error or FFA_SUCCESS_32 without further values are used
on success

core: thread_spmc.c: add set_simple_ret_val()

Simplify common FFA_ERRROR/FFA_SUCCESS_32 patterns where an error code
is returned on error or FFA_SUCCESS_32 without further values are used
on success.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit

core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit (V), which is not proper way when clearing PTE. Fix it by only
honoring pte_bits parameter, which may be constructed in
mattr_to_pte_bits().

The core_mmu_ptp_create() is used to create non-leaf PTE, which points
to the next level of the page table. According to RISC-V privilege Spec,
non-leaf PTE only needs V bit. Therefore, we just give the V bit to
core_mmu_pte_create() when we want to create non-leaf PTE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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