plat-mediatek: add support to extend MAX_XLAT_TABLE

When using the reserved virtual memory space, it is necessary to
increase MAX_XLAT_TABLE based on its size.

Signed-off-by: Gavin Liu <gavin.liu@m

plat-mediatek: add support to extend MAX_XLAT_TABLE

When using the reserved virtual memory space, it is necessary to
increase MAX_XLAT_TABLE based on its size.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64.h: fix compile error with Clang

Clang 18.1.6 fails to compile OP-TEE OS with the following error:

CC out/arm/core/arch/arm/kernel/vfp.o
In file included from core/arch/arm/kernel/vfp

arm64.h: fix compile error with Clang

Clang 18.1.6 fails to compile OP-TEE OS with the following error:

CC out/arm/core/arch/arm/kernel/vfp.o
In file included from core/arch/arm/kernel/vfp.c:6:
In file included from core/arch/arm/include/arm.h:137:
core/arch/arm/include/arm64.h:455:1: error: expected readable system register
455 | DEFINE_U32_REG_READWRITE_FUNCS(fpcr)
| ^
core/arch/arm/include/arm64.h:436:3: note: expanded from macro 'DEFINE_U32_REG_READWRITE_FUNCS'
436 | DEFINE_U32_REG_READ_FUNC(reg) \
| ^
core/arch/arm/include/arm64.h:430:3: note: expanded from macro 'DEFINE_U32_REG_READ_FUNC'
430 | DEFINE_REG_READ_FUNC_(reg, uint32_t, reg)
| ^
core/arch/arm/include/arm64.h:417:15: note: expanded from macro 'DEFINE_REG_READ_FUNC_'
417 | asm volatile("mrs %0, " #asmreg : "=r" (val64)); \
| ^
<inline asm>:1:10: note: instantiated into assembly here
1 | mrs x8, fpcr
| ^

...and similar ones for fpcr write, as well as fpsr read and write.

Clang 12.0.0 does not have any problem with this code which makes me
think that it's a Clang/LLVM issue.

Work around the problem by using the coded system register identifiers
S3_3_c4_c4_0 and S3_3_c4_c4_1 instead of fpcr and fpsr, respectively.
The values 3-3-4-4-0 and 3-3-4-4-1 are taken from the Arm ARM sections
C.5.2.8 and C.5.2.9.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix race condition on TA/PTA/StMM context loading

Fix race condition on creation of a context for single instance TAs,
PTAs or StMM application. Such race condition could occur and lead to
dup

core: fix race condition on TA/PTA/StMM context loading

Fix race condition on creation of a context for single instance TAs,
PTAs or StMM application. Such race condition could occur and lead to
duplicated contexts if connected close enough that they are created
after tee_ta_init_session() calls tee_ta_init_session_with_context()
and before the context are added in the centralized context list.

This is realized by keeping tee_ta_mutex held while tee_ctxes list is
looked up for matching a context or a new context is added into that
list with its .is_initializing field activated. For that purpose
user TA and StMM application initialization function are split in
2 functions, the 2nd one used to finalizes the context creation
started in the 1st function.

By the way, add inline description comments and fix indentation issues
in uaer_ta.h and remove the inline comment in pseudo_ta.c that refers
to TA loading whereas the function relates to PTA contexts creation.

Closes: https://github.com/OP-TEE/optee_os/issues/6801
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: make is_initializing field a generic service context

Replace fields is_initializing from struct user_mode_ctx and
struct stmm_ctx with a common new field is_initialing in generic
struct tee_ta

core: make is_initializing field a generic service context

Replace fields is_initializing from struct user_mode_ctx and
struct stmm_ctx with a common new field is_initialing in generic
struct tee_ta_ctx so that it can be used in generic context loading
functions for contexts which initialization is done with tee_ta_mutex
released.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: plat-corstone1000: Remove MMCOMM buffer address

Remove MMCOMM buffer address and mapping, as it is not
being used anymore

Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

core: plat-corstone1000: Remove MMCOMM buffer address

Remove MMCOMM buffer address and mapping, as it is not
being used anymore

Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Emekcan Aras <emekcan.aras@arm.com>

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core: rename tee_mm_shm to core_virt_shm_pool

Rename tee_mm_shm to core_virt_shm_pool to make it clear that it handles
virtual memory allocations for shared memory.

Signed-off-by: Jens Wiklander <j

core: rename tee_mm_shm to core_virt_shm_pool

Rename tee_mm_shm to core_virt_shm_pool to make it clear that it handles
virtual memory allocations for shared memory.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: rename tee_mm_vcore to core_virt_mem_pool

Rename tee_mm_vcore to core_virt_mem_pool to make it clear that it
handles virtual memory allocations.

Signed-off-by: Jens Wiklander <jens.wiklander@

core: rename tee_mm_vcore to core_virt_mem_pool

Rename tee_mm_vcore to core_virt_mem_pool to make it clear that it
handles virtual memory allocations.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: move manifest DT functions to dt.c

This moves functions to handle manifest DT, used as a SP (secure partition)
manifest via FF-A interface, to core/kernel/dt.c and their definitions
to

core: kernel: move manifest DT functions to dt.c

This moves functions to handle manifest DT, used as a SP (secure partition)
manifest via FF-A interface, to core/kernel/dt.c and their definitions
to dt.h.
manifest DT is dependent with CORE_FFA that depends on CFG_DT, as the same
as dt.c.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: plat-virt: switch to dynamic shared memory

Enable dynamic shared memory for QEMU virt machine.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@an

riscv: plat-virt: switch to dynamic shared memory

Enable dynamic shared memory for QEMU virt machine.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: riscv: Add a reserved-memory node for static shared memory

To prevent Linux from using static shared memory, include the
dedicated reserved-memory node in the device tree.

Signed-off-by: Alvi

core: riscv: Add a reserved-memory node for static shared memory

To prevent Linux from using static shared memory, include the
dedicated reserved-memory node in the device tree.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: kernel: factor out shared memory boot-time helpers

The static and dynamic shared memory helpers used for boot-time
reservation/registration are non-architecture-specific. Moving
them into the

core: kernel: factor out shared memory boot-time helpers

The static and dynamic shared memory helpers used for boot-time
reservation/registration are non-architecture-specific. Moving
them into the generic boot.c file will help avoid duplicated code
and improve maintainability.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: mm: move mobj_dyn_shm.c to mm

To enable RISC-V platforms to utilize dynamic shared memory,
relocate the non-architecture-specific mobj_dyn_shm.c to the
mm directory.

Signed-off-by: Alvin Chan

core: mm: move mobj_dyn_shm.c to mm

To enable RISC-V platforms to utilize dynamic shared memory,
relocate the non-architecture-specific mobj_dyn_shm.c to the
mm directory.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-hikey: make DRAM0_SIZE and DRAM0_SIZE_NSEC configurable

DRAM0_SIZE is now defined as CFG_TZDRAM_START, allowing
for dynamic configuration.

DRAM0_SIZE_NSEC is modified to calculate the size rel

plat-hikey: make DRAM0_SIZE and DRAM0_SIZE_NSEC configurable

DRAM0_SIZE is now defined as CFG_TZDRAM_START, allowing
for dynamic configuration.

DRAM0_SIZE_NSEC is modified to calculate the size relative
to DRAM0_BASE.

Signed-off-by: Wen Bin <a1231512a@163.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-mediatek: fix enforcement of SWRNG configuration on MT7988

Small fix: $(call force,CFG_WITH_SOFTWARE_PRNG,Y) should be lowercase
'y' so that the conditional check in core/crypto/sub.mk in

core: plat-mediatek: fix enforcement of SWRNG configuration on MT7988

Small fix: $(call force,CFG_WITH_SOFTWARE_PRNG,Y) should be lowercase
'y' so that the conditional check in core/crypto/sub.mk includes
the correct source file rng_fortuna.c instead of rng_hw.c, which is
unimplemented for this platform and causes build failure.

Fixes: 58dbe3dff530 ("plat-mediatek: add support for MT7988 SoC")
Signed-off-by: Charles Herz <herzc@umich.edu>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: fix arguments passed to calloc in alloc_merged_pgt_array()

An error was reported when compiling with GCC14 on this calloc:

core/arch/arm/mm/tee_pager.c: In function 'alloc_merged_pgt_a

core: pager: fix arguments passed to calloc in alloc_merged_pgt_array()

An error was reported when compiling with GCC14 on this calloc:

core/arch/arm/mm/tee_pager.c: In function 'alloc_merged_pgt_array':
core/arch/arm/mm/tee_pager.c:934:35: warning: 'calloc' sizes specified
with 'sizeof' in the earlier argument and not in the later argument
[-Wcalloc-transposed-args]
934 | pgt_array = calloc(sizeof(struct pgt *), pgt_count);
| ^~~~~~

Looking at the code, it seems that pgt_count and sizeof(struct pgt *)
are inverted.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Fixes: 60e367146042 ("core: pager fix alloc_merged_pgt_array()")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Fix store 32-bit thread_core_local flags

The thread_core_local flags is a 32-bit variable. Thus, we must
explicitly use "sw" instruction, which means store 32-bit value into
specific me

core: riscv: Fix store 32-bit thread_core_local flags

The thread_core_local flags is a 32-bit variable. Thus, we must
explicitly use "sw" instruction, which means store 32-bit value into
specific memory address, to operate the thread_core_local flags.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driv

drivers: Add FFA_CONSOLE based console driver for log

This console driver uses FFA_CONSOLE ABI to write the trace logs.

If CFG_FFA_CONSOLE is enabled, OP-TEE will try to initialize the console
driver that uses FFA interface to print trace logs.

Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: spmc: fix direct request handler

The FF-A direct request handling has an error: if the destination ID is
the SPMC ID, the handler is trying to forward the message to an SP with
this ID, which

core: spmc: fix direct request handler

The FF-A direct request handling has an error: if the destination ID is
the SPMC ID, the handler is trying to forward the message to an SP with
this ID, which is obviously non-existent so this gives an error.

Fixes: 19ad526cb139 ("core: spmc, sp: cleanup FF-A ID handling")
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

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core: arm: use fdt64_ld() to read possibly unaligned kaslr-seed

Read possibly unaligned kaslr-seed using `fdt64_ld()`
to avoid ubsan panic while booting with `CFG_CORE_ASLR=y`

Acked-by: Jens Wiklan

core: arm: use fdt64_ld() to read possibly unaligned kaslr-seed

Read possibly unaligned kaslr-seed using `fdt64_ld()`
to avoid ubsan panic while booting with `CFG_CORE_ASLR=y`

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Abhishek Revadekar <abhishek.rvdkr@yahoo.com>

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core: arm64: fix ce_aes_xts_{de,en}crypt()

In ce_aes_xts_encrypt() and ce_aes_xts_decrypt(), if the main interleave
loop (.LxtsencNx or .LxtsdecNx) ends with all blocks completed the v7
register doe

core: arm64: fix ce_aes_xts_{de,en}crypt()

In ce_aes_xts_encrypt() and ce_aes_xts_decrypt(), if the main interleave
loop (.LxtsencNx or .LxtsdecNx) ends with all blocks completed the v7
register doesn't hold the needed .Lxts_mul_x needed to compute the next
tweak correctly. So fix this by loading .Lxts_mul_x in v7 before ending
the loop.

Fixes: 06d2e4167a6b ("core: add accelerated AES routines")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: remove CFG_PL310_LOCKED

When locking the PL310 cache, it behaves as disable which lead to poor
performances in Linux.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-b

plat-sam: remove CFG_PL310_LOCKED

When locking the PL310 cache, it behaves as disable which lead to poor
performances in Linux.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: plat-virt: Enable CFG_HWRNG_PTA

Enable CFG_HWRNG_PTA with the implementation of the RISC-V
Zkr driver which provides the hardware entropy source.

Signed-off-by: Alvin Chang <alvinga@andestec

riscv: plat-virt: Enable CFG_HWRNG_PTA

Enable CFG_HWRNG_PTA with the implementation of the RISC-V
Zkr driver which provides the hardware entropy source.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Add seed CSR detection helper

Any attempted access to unimplemented or restricted CSRs will
raise an illegal instruction, so we can set up a temporary
trap handler to validate if the us

core: riscv: Add seed CSR detection helper

Any attempted access to unimplemented or restricted CSRs will
raise an illegal instruction, so we can set up a temporary
trap handler to validate if the use of CSRs is allowed in
the privileged mode where OP-TEE OS is running. Add a helper
for this specific purpose.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add IPCC1/2 nodes in stm32mp251.dtsi

Add Inter-Processor Communication Controller 1/2(IPCC) nodes and default
disable them.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.c

dts: stm32: add IPCC1/2 nodes in stm32mp251.dtsi

Add Inter-Processor Communication Controller 1/2(IPCC) nodes and default
disable them.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: conf: support IPCC driver

Default enable IPCC driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carri

plat-stm32mp2: conf: support IPCC driver

Default enable IPCC driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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