core: add code for the interrupt framework

With this commit, we add three more GIC APIs for the kernel of OPTEE-OS:
itr_raise_sgi : can raise software generate interrupt(SGI) from secure
world to no

core: add code for the interrupt framework

With this commit, we add three more GIC APIs for the kernel of OPTEE-OS:
itr_raise_sgi : can raise software generate interrupt(SGI) from secure
world to no-secure world, or secure world to secure world. It's a quick
communication between different worlds and different cores. Because SGI
is using the GIC N-N model, so with this API, every core can receive
the interrupt if want.

itr_raise_pi : can trigger the peripheral interrupt with the corresponding
interrupt number. When sending it to N cores, just one core can receive
the effective interrupt.

itr_set_affinity : can target the peripheral interrupt to the core you
want, it means that one can bind the interrupt to the corresponding core
use this API.

The usage may as follow:
itr_raise_sgi(11, 0x1 << 1)
it will raise SGI11 to core 1, and if you want not only core 1 can receive
SGI11 but also core 2, then you can change the code to
itr_raise_sgi(11, 0x1 << 1 || 0x1 << 2).

itr_set_affinity(61, 0x1 << 1)
itr_raise_pi(61)
These two APIs may use together, the operation set_affinity set the PI61
can just sent to core 1, then raise_pi, core 1 will receive the peripheral
interrupt 61.

Signed-off-by: Guanchao Liang <liang.guanchao@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU)
[Update commit author to be same as S-o-b: above]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core/armv7: cleanup bootargs

In non-A-TF boot modes, OP-TEE core expects some boot arguments:
- nonsecure entry point, default expected from core register LR.
- pagestore address, when pager is enab

core/armv7: cleanup bootargs

In non-A-TF boot modes, OP-TEE core expects some boot arguments:
- nonsecure entry point, default expected from core register LR.
- pagestore address, when pager is enable, from core register R0.
- devicetree address, when DT is enable, from core register R2.

Some non-A-TF booted platform rely on u-boot has bootloader, and
expect u-boot to boot both linux and op-tee. armv7/linux expects the
following boot arguments:
- machine ID, expected from core register R1.
- devicetree address from core register R2.

Before this patch, some platform used CFG_TEE_GDB_BOOT together with
CFG_BUILT_IN_ARGS to both provide op-tee core boot arguments, and
relay linux argument from op-tee entry to linux kernel entry
(nonsecure entry).

This change proposes to rationalize a bit. Both linux and optee expect
device tree from register R2. op-tee could relay machine ID (R1).

This change removes CFG_TEE_GDB_BOOT and CFG_BUILT_IN_ARGS that are now
deprecated.

This change still supports CFG_PAGEABLE_ADDR, CFG_DT_ADDR and
CFG_NS_ENTRY_ADDR to statically define the pagestore, device tree
and nonsecure entry. These can be defined independently.

Since this change, if CFG_WITH_ARM_TRUSTED_FW is not enable, the
standard boot arguments (registers R1 and R2 at optee entry) are
propagated to the non secure entry.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core/armv7: clear 4th arg of secondary boot cores nonsecure entry

Secondary boot cores shall clean cpu register R4 before leaving secure.
R4 is the 4th argument propagated to non-secure entry by opt

core/armv7: clear 4th arg of secondary boot cores nonsecure entry

Secondary boot cores shall clean cpu register R4 before leaving secure.
R4 is the 4th argument propagated to non-secure entry by optee monitor.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: fix stack setup at secondary core entry

stack_tmp_offset is required by secondary boot cores before
pager is initialized.

Fixes: e56a56428def ("core: sm: use stack_tmp for sm_from_nsec")
Sign

core: fix stack setup at secondary core entry

stack_tmp_offset is required by secondary boot cores before
pager is initialized.

Fixes: e56a56428def ("core: sm: use stack_tmp for sm_from_nsec")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: sm: use stack_tmp for sm_from_nsec()

As the C function sm_from_nsec() used by the secure monitor is expected
to be extended over time it needs a larger stack. With this patch the
secure monito

core: sm: use stack_tmp for sm_from_nsec()

As the C function sm_from_nsec() used by the secure monitor is expected
to be extended over time it needs a larger stack. With this patch the
secure monitor uses stack_tmp. The first part of stack_tmp is
permanently reserved for secure and non-secure contexts.

Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi3)
Tested-by: Andrew F. Davis <afd@ti.com> (plat-ti)
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm-b2260)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7 & v8)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: redesign secure monitor

The secure monitor is redesigned to make it easier to register services.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jen

core: redesign secure monitor

The secure monitor is redesigned to make it easier to register services.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: add mov_imm assembly macro

Adds mov_imm assembly macro to load 32-bit immediate values into a
register.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens

core: arm32: add mov_imm assembly macro

Adds mov_imm assembly macro to load 32-bit immediate values into a
register.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: fix compile error

Error log:
core/arch/arm/plat-imx/conf.mk:26: *** missing separator. Stop.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

core: imx: fix compile error

Error log:
core/arch/arm/plat-imx/conf.mk:26: *** missing separator. Stop.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix ta_private_vmem support

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: fix support of TA_FLAG_CACHE_MAINTENANCE

Allow loaded TAs to set the property TA_FLAG_CACHE_MAINTENANCE.

TAs are allowed to request cache maintenance operations only on
the memory buffers pas

core: fix support of TA_FLAG_CACHE_MAINTENANCE

Allow loaded TAs to set the property TA_FLAG_CACHE_MAINTENANCE.

TAs are allowed to request cache maintenance operations only on
the memory buffers passed as parameters. They are not allowed to
do cache maintenance on TA private data.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libutee extension: check-access-right for secure/nonsec permissions

Define TEE_MEMORY_ACCESS_NONSECURE and TEE_MEMORY_ACCESS_SECURE are
extensions of the flag bitfield argument of TEE_CheckMemoryAcc

libutee extension: check-access-right for secure/nonsec permissions

Define TEE_MEMORY_ACCESS_NONSECURE and TEE_MEMORY_ACCESS_SECURE are
extensions of the flag bitfield argument of TEE_CheckMemoryAccessRights().
Once one of these is set, core checks the secure mapping attribute.

Note: if both are set, it's obviously an caller error. Implementation
will return a TEE_ERROR_ACCESS_DENIED.

Include tee_api_defines_extensions.h from tee_internal_api_extensions.h
so that TAs only have to include tee_internal_api_extensions.h to access
extensions resources.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: boot up secondary cores more reliable

Set CORE[x]_RST bit when release secondary cores to make it
more reliable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere

core: imx: boot up secondary cores more reliable

Set CORE[x]_RST bit when release secondary cores to make it
more reliable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: switch to use c code for PL310

1. Add a new file imx_pl310.c for arm_cl2_config and arm_cl2_enable.

2. For i.MX6Q, CFG_PL310 is defined and arm_cl2_config is implemented.
In arm_cl2_c

core: imx: switch to use c code for PL310

1. Add a new file imx_pl310.c for arm_cl2_config and arm_cl2_enable.

2. For i.MX6Q, CFG_PL310 is defined and arm_cl2_config is implemented.
In arm_cl2_config, all ways are invalidated, but it does not follow
the rules to wait all ways to be invalidated. So In the following
call to inval_cache_vrange, arm_cl2_cleaninvbypa will trigger SLVERR.

This is because the first invalidation operation not finished in
background, and another invalidation is issued to PL310. So switch
to use arm_cl2_invbyway which will wait until invalidation finished.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix mapping init debug trace

Before this change, debug trace shows wrong virtual address range.

Confusion comes from the 'struct tee_mmap_region':

va Start address of the virtual

core: fix mapping init debug trace

Before this change, debug trace shows wrong virtual address range.

Confusion comes from the 'struct tee_mmap_region':

va Start address of the virtual 'region' where to map.
Aligned on 'region' alignment constraint.
region_size Byte size of the virtual 'region' where to map.
pa Physical start address of the *mapped* buffer.
size Byte size of the *mapped* buffer.

The virtual start address of the *mapped* buffer is not stored in the
structure. It must be computed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core: fix 'flow' traces in pager

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Etienne Carriere <etienne.car

core: fix 'flow' traces in pager

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: keep plat_cpu_reset_early() unpaged

Keep plat_cpu_reset_early() in unpaged area since it needs to be always
available.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signe

core: pager: keep plat_cpu_reset_early() unpaged

Keep plat_cpu_reset_early() in unpaged area since it needs to be always
available.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix virt2phys conversion before core main inits

Before this change, virtual-to-physical address conversion with pager
enable was corrupted until TEE executes its main inits. This change
allow

core: fix virt2phys conversion before core main inits

Before this change, virtual-to-physical address conversion with pager
enable was corrupted until TEE executes its main inits. This change
allow v2p conversion in the TEE RAM during core early inits.

Debug mode is a configuration where v2p are done before core main inits.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU, b2260)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU)

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mm: use paddr_t to support both 32- and 64-bit arch

Adjust low and high parameter and pool entry type to accurately reflect
architectural sizes and additionally, correct other related uses of uint32

mm: use paddr_t to support both 32- and 64-bit arch

Adjust low and high parameter and pool entry type to accurately reflect
architectural sizes and additionally, correct other related uses of uint32_t
that should be paddr_t.

Signed-off-by: Philip Attfield <opensource@sequiturlabs.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

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core/libutee: perform cleanup for magic "4"

Perform cleanup for magic "4" constant that represents amount of tee
params

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Etienne Ca

core/libutee: perform cleanup for magic "4"

Perform cleanup for magic "4" constant that represents amount of tee
params

Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: beautify CFG_BOOT_SYNC_CPU in generic_entry_a32.S

convert cpu_is_ready(), wait_primary(), wait_secondary() into
marcos. Prevents dummy empty routines when CFG_BOOT_SYNC_CPU is not set.

Signed

core: beautify CFG_BOOT_SYNC_CPU in generic_entry_a32.S

convert cpu_is_ready(), wait_primary(), wait_secondary() into
marcos. Prevents dummy empty routines when CFG_BOOT_SYNC_CPU is not set.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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plat-stm: define default configuration when pager is enable

plat-stm can optionally build with CFG_WITH_PAGER=y. Pager RAM is
defined from CFG_CORE_TZSRAM_EMUL_START and CFG_CORE_TZSRAM_EMUL_SIZE.

plat-stm: define default configuration when pager is enable

plat-stm can optionally build with CFG_WITH_PAGER=y. Pager RAM is
defined from CFG_CORE_TZSRAM_EMUL_START and CFG_CORE_TZSRAM_EMUL_SIZE.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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core: beautify generic_entry_a32.S

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere

core: beautify generic_entry_a32.S

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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core: fix generic ARMv7/AArch32 boot against SMP

This change flushes cache before primary releases secondary core
to insure they find the right data in memory.

Case CFG_PL310_LOCK: wait all seconda

core: fix generic ARMv7/AArch32 boot against SMP

This change flushes cache before primary releases secondary core
to insure they find the right data in memory.

Case CFG_PL310_LOCK: wait all secondary cores have completed their
inits before locking PL310 lines.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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core: fix generic ARMv7/AArch32 boot against PL310

Follow ARM recommendation for PL310 outer cache maintenance.
- caches invalidate: invalidate L2 then L1.
- caches flush: clean L1 then flush L2, th

core: fix generic ARMv7/AArch32 boot against PL310

Follow ARM recommendation for PL310 outer cache maintenance.
- caches invalidate: invalidate L2 then L1.
- caches flush: clean L1 then flush L2, then flush L1.

To ease main sequence, define macros of cache operations.

inval/flush_cache_vrange() with PL310 in early boot requires va=pa.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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core: fix pager against SMP on non A-TF booted op-tee

plat_cpu_reset_late() must be moved to the unpaged sections. It is
called by secondary core when entering core after primary core inits
are done

core: fix pager against SMP on non A-TF booted op-tee

plat_cpu_reset_late() must be moved to the unpaged sections. It is
called by secondary core when entering core after primary core inits
are done, hence 'init' section may have been unmapped.

Cleanup: move plat_cpu_reset_early/_late() out of generic_entry_a32.S.

Change CFG_PL310_LOCKED sequence: flush content instead of rude
full invalidation. This is required since core inits may write outside
TEE RAM and PL310 must not discard new content.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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