core: add pgt_clear_ctx_range()

Adds pgt_clear_ctx_range() which clears the corresponding entries in
the active or cached translation tables of user mode context.

Reviewed-by: Etienne Carriere <eti

core: add pgt_clear_ctx_range()

Adds pgt_clear_ctx_range() which clears the corresponding entries in
the active or cached translation tables of user mode context.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: check snprintf() return value in add_res_mem_dt_node()

Adds a check for the return value from snprintf() in
add_res_mem_dt_node(). In case snprintf() has failed of truncates the
output a debug

core: check snprintf() return value in add_res_mem_dt_node()

Adds a check for the return value from snprintf() in
add_res_mem_dt_node(). In case snprintf() has failed of truncates the
output a debug warning in the log.

This fixes coverity scan:
CID 1501804 (#1 of 1): Unchecked return value (CHECKED_RETURN)

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mobj: fix memory leak

dynamic shared memory is not being released leading to an out of
memory condition.

Issue triggered during tests exporting the cryptographic random
generator to the REE (

core: mobj: fix memory leak

dynamic shared memory is not being released leading to an out of
memory condition.

Issue triggered during tests exporting the cryptographic random
generator to the REE (Linux) and then reading the value via the device
interface (/dev/hwrng).

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-ls: add i2c driver for NXP LS Platforms

I2C Driver compilation is enabled by default for LX2160A-RDB
and LX2160A-QDS.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jens W

plat-ls: add i2c driver for NXP LS Platforms

I2C Driver compilation is enabled by default for LX2160A-RDB
and LX2160A-QDS.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Clement Faure <clement.faure@nxp.com>

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build: core: add missing dependencies when generating assembly constants

The header file <generated/asm-defines.h> is created at build time. It
contains macro definitions for various offsets in C st

build: core: add missing dependencies when generating assembly constants

The header file <generated/asm-defines.h> is created at build time. It
contains macro definitions for various offsets in C structures and is
especially useful for use from assembler code. It is generated from
asm-defines.c, which includes a number of header files, of which two
are also generated at build time: <generated/arm32_sysreg.h> and
<generated/arm32_gicv3_sysreg.h>.

These dependencies are expressed nowhere in the makefiles and therefore
build errors can result. For example:

$ make out/arm-plat-vexpress/core/include/generated/.asm-defines.s
CHK out/arm-plat-vexpress/conf.mk
UPD out/arm-plat-vexpress/conf.mk
CHK out/arm-plat-vexpress/include/generated/conf.h
UPD out/arm-plat-vexpress/include/generated/conf.h
CC out/arm-plat-vexpress/core/include/generated/.asm-defines.s
In file included from core/arch/arm/include/arm.h:99,
from core/arch/arm/include/kernel/thread.h:12,
from core/arch/arm/kernel/asm-defines.c:8:
core/arch/arm/include/arm32.h:167:10: fatal error: generated/arm32_sysreg.h: No such file or directory
167 | #include <generated/arm32_sysreg.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.

The error in [1] is believed to have the same root cause: during
parallel build the generated header file might have been created by one
job but not yet written to when another job would open it. The compiler
would see an empty file, thus the missing declarations.

Add the missing dependencies via a new variable at the location where
asm-defines.c is added to the build.

Note that the other core .c files depending on these generated sysreg
headers are not affected because their .o files explicitly depend on
FORCE-GENSRCcore (which generates the headers).

Link: [1] https://ci.linaro.org/job/ledge-oe-premerge-ci/182/DISTRO=rpb,MACHINE=ledge-ti-am572x,label=docker-buster-amd64/console
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat: rcar: Obtain memory layout from DT

Since the ATF is passing a DT fragment to OpTee-OS, parse the memory
information from this DT fragment. This makes it possible to run the
OpTee-OS on any mem

plat: rcar: Obtain memory layout from DT

Since the ATF is passing a DT fragment to OpTee-OS, parse the memory
information from this DT fragment. This makes it possible to run the
OpTee-OS on any memory layout instead of the few hard-coded options.
Switch the default platform to this DT based approach, but retain the
legacy platforms as well for backward compatibility.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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plat: rcar: Derive core map from PRR

Instead of hard-coding the core count and the core ID mapping,
derive this information from the PRR register. All R-Car3 SoCs
have either one or two 4-core CPU c

plat: rcar: Derive core map from PRR

Instead of hard-coding the core count and the core ID mapping,
derive this information from the PRR register. All R-Car3 SoCs
have either one or two 4-core CPU clusters composed of CA53 or
CA57, except for M3W/M3W+, which has two CA57s and four CA53s.

So the approach here is to always set core count to 8, read out
PRR register once on boot, and then calculate the core ID using
CorePos = CoreId + (ClusterId << (IsM3W ? 1 : 0))

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

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core: mobj: fixup undefined mobj_mapped_shm_alloc

Provide a function definition when CFG_CORE_DYN_SHM is not configured.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jens Wi

core: mobj: fixup undefined mobj_mapped_shm_alloc

Provide a function definition when CFG_CORE_DYN_SHM is not configured.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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virt: round down TA RAM memory size to page size

It is possible that get_ta_ram_size() would return size which is not
aligned to a small page size. This will cause panic in core_init_mmu_prtn()
func

virt: round down TA RAM memory size to page size

It is possible that get_ta_ram_size() would return size which is not
aligned to a small page size. This will cause panic in core_init_mmu_prtn()
function.

To fix this we need to round down calculated value to a page size.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: dcp: add DCP support

The Data Co-Processor (DCP) provides hardware acceleraiton for
cryptographic algorithms. The features of DCP are:
- AES128 ECB and CBC
- SHA1, SHA256
- AES128-CMAC a

drivers: dcp: add DCP support

The Data Co-Processor (DCP) provides hardware acceleraiton for
cryptographic algorithms. The features of DCP are:
- AES128 ECB and CBC
- SHA1, SHA256
- AES128-CMAC algorithm
- SRAM key storage
- HUK generation

This driver adds DCP support for the following platforms:
- imx6slevk
- imx6sllevk
- imx6ullevk
- imx6ulzevk

Signed-off-by: Remi Koman <remi.koman@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: csu: enable DCP protection

Enable DCP protection in the CSU for the following platforms:
- imx6slevk
- imx6sllevk
- imx6ullevk
- imx6ulzevk

Signed-off-by: Clement Faure <clement.fa

drivers: csu: enable DCP protection

Enable DCP protection in the CSU for the following platforms:
- imx6slevk
- imx6sllevk
- imx6ullevk
- imx6ulzevk

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add dcache_get_line_size() function

Add dcache_get_line_size() function to get cache line size for ARM32 and
ARM64 platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by:

core: add dcache_get_line_size() function

Add dcache_get_line_size() function to get cache line size for ARM32 and
ARM64 platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: clarify tlbi_mva_range()

Clarifies tlbi_mva_range() with a full description of the interface at
the declaration of the function. The supplied VA range must be aligned
on the supplied granulari

core: clarify tlbi_mva_range()

Clarifies tlbi_mva_range() with a full description of the interface at
the declaration of the function. The supplied VA range must be aligned
on the supplied granularity.

The implementation is updated to take full advantage of this restriction
together with an additional assert.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove deprecated core_tlb_maintenance()

Removes the deprecated and unused function core_tlb_maintenance().

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander

core: remove deprecated core_tlb_maintenance()

Removes the deprecated and unused function core_tlb_maintenance().

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ls: lx2160aqds: get GIC base address from dtb

CFG_EMBED_DT option is enabled by default for LX2160A-QDS
GIC base address was hardcoded for LX2160A-QDS,
now will get the base address from dtb f

core: ls: lx2160aqds: get GIC base address from dtb

CFG_EMBED_DT option is enabled by default for LX2160A-QDS
GIC base address was hardcoded for LX2160A-QDS,
now will get the base address from dtb file.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: dts: add DTS files for LX2160A-RDB

Add dts file for LX2160A-QDS Platform.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

core: ls: add LX2160A-QDS platform

Add support for Layerscape® LX2160A-QDS from NXP.
Dynamic shared memory is also enabled.

Signed-off-by: Manish Tomar <manish.tomar@nxp.com>
Signed-off-by: Sahil M

core: ls: add LX2160A-QDS platform

Add support for Layerscape® LX2160A-QDS from NXP.
Dynamic shared memory is also enabled.

Signed-off-by: Manish Tomar <manish.tomar@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: ls: lx2160ardb: get GIC base address from dtb

CFG_EMBED_DT option is enabled by default for LX2160A-RDB
GIC base address was hardcoded for LX2160A-RDB,
now will get the base address from dtb f

core: ls: lx2160ardb: get GIC base address from dtb

CFG_EMBED_DT option is enabled by default for LX2160A-RDB
GIC base address was hardcoded for LX2160A-RDB,
now will get the base address from dtb file.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: ls: Remove GIC initialization for ARM-TF based platforms

On ARMv8, GIC configuration is initialized in ARM-TF

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Sahil Malhotr

core: ls: Remove GIC initialization for ARM-TF based platforms

On ARMv8, GIC configuration is initialized in ARM-TF

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: dts: add DTS files for LX2160A-RDB

LX2160A-RDB will be compiled with Embedded DTB support.
Add dts file for LX2160A-RDB Platform.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-

core: dts: add DTS files for LX2160A-RDB

LX2160A-RDB will be compiled with Embedded DTB support.
Add dts file for LX2160A-RDB Platform.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: ls: lx2160ardb: Add regions for dynamic shared memory

To enable use of dynamic shared memory, DDR regions
need to be added in the platform MMU map.

Signed-off-by: Ruchika Gupta <ruchika.gupta

core: ls: lx2160ardb: Add regions for dynamic shared memory

To enable use of dynamic shared memory, DDR regions
need to be added in the platform MMU map.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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console: lx2160A: fix uart clock and baud rate

Currently there are garbled messages from OP-TEE due to
assumption that platform clock is always 700MHz. This is
not correct as LX2 supports variable p

console: lx2160A: fix uart clock and baud rate

Currently there are garbled messages from OP-TEE due to
assumption that platform clock is always 700MHz. This is
not correct as LX2 supports variable platform frequency.
It could be one of the 600, 650, 700, 750 Mhz based on
the RCW configuration.

Ideally OPTEE should read RCW registers from Global Utilities
Register block and derive the uart clock based on platform pll
frequency. But there is no need for this as Baud Rate is already
configured in PL011 by the previous boot stages in TF-A.
This fix calls pl011_init() with zero for baud rate => It won't be
reinitalized in OP-TEE.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: fix icache_inv_user_range()

Prior to this patch with CFG_WITH_PAGER=y, CFG_WITH_LPAE=y and
CFG_CORE_UNMAP_CORE_AT_EL0=n icache_inv_user_range() crashes with a
prefetch abort due to TTBR0 being

core: fix icache_inv_user_range()

Prior to this patch with CFG_WITH_PAGER=y, CFG_WITH_LPAE=y and
CFG_CORE_UNMAP_CORE_AT_EL0=n icache_inv_user_range() crashes with a
prefetch abort due to TTBR0 being configured with an invalid value.
This happens due to an error in the ifdef logic using an uninitialized
register.

Fix this by using the correct register.

Fixes: c4a57390edef ("core: pager: use icache_inv_user_range()")
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix shared memory buffer rpc allocation

When dynamic shared memory has been configured, contiguous shared
memory regions outside reserved SHM need to be included in the
allocation pool.

To ke

core: fix shared memory buffer rpc allocation

When dynamic shared memory has been configured, contiguous shared
memory regions outside reserved SHM need to be included in the
allocation pool.

To keep the implementation simple, we will restrict the size of these
allocations to a single page; we can then leverage the mechanism used
for the allocation of arguments.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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link: make section size definitions relocation-proof

Value of define VCORE_UNPG_RW_SZ is determined by linker script and
provided to C code as a symbol value (__vcore_unpg_rw_size). This is a
standa

link: make section size definitions relocation-proof

Value of define VCORE_UNPG_RW_SZ is determined by linker script and
provided to C code as a symbol value (__vcore_unpg_rw_size). This is a
standard way of sharing linker variables with C code, which is described in
ld manual.

Problem is that linker sometimes makes those symbols relocatable and ASLR
code then moves them to random places with rest of the OP-TEE image.

For example, on build for RCAR platform I am getting those entries in
relocation section:

[...]
000000004415b120 R_AARCH64_RELATIVE *ABS*+0x0000000044100180
000000004415af60 R_AARCH64_RELATIVE *ABS*+0x000000004415fc48
000000004415afb0 R_AARCH64_RELATIVE *ABS*+0x00000000000a4000 <======
000000004415aef8 R_AARCH64_RELATIVE *ABS*+0x000000004415c000
[...]

From programmer's point of view this looks like "constant" VCORE_UNPG_RW_SZ
has random value every boot.

Obvious approach is to provide section end address and then calculate size
on C side:

#define VCORE_UNPG_RW_SZ ((size_t)(__vcore_unpg_rx_end -
__vcore_unpg_rx_start))

But with this approach compiler can't initialize constant values in
definitions like

register_phys_mem_ul(MEM_AREA_TEE_RAM_RW, VCORE_UNPG_RW_PA,
VCORE_UNPG_RW_SZ);

from core_mmu.c.

Basically, this leads to following constraints:

1. If we calculate section size in linker script, then compiler can use
it as a constant expression, but this value may be mangled by ASLR
at run-time.

2. We can't calculate section size in C code, because this value can't be
used as a constant expression.

This patch provides a workaround around this issue by providing two sets of
definitions: old _SZ definition is renamed to _SZ_UNSAFE and it should be
used only in places where a constant expression is required and provided it
is referenced only before dynamic relocations have been applied, while the
new _SZ definition can be used in all other situations.

Value of _new SZ is obtained by deducting section start address from end
address. Additional linker symbols are introduced to provide section end
addresses.

Fixes: 170e9084a84f ("core: add support for CFG_CORE_ASLR")
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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