1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright 2018 NXP 4 * Copyright (C) 2015 Freescale Semiconductor, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <platform_config.h> 31 32 #include <arm.h> 33 #include <console.h> 34 #include <drivers/gic.h> 35 #ifdef CFG_PL011 36 #include <drivers/pl011.h> 37 #else 38 #include <drivers/ns16550.h> 39 #endif 40 #include <io.h> 41 #include <kernel/boot.h> 42 #include <kernel/misc.h> 43 #include <kernel/panic.h> 44 #include <kernel/thread.h> 45 #include <kernel/tz_ssvce_def.h> 46 #include <mm/core_memprot.h> 47 #include <sm/optee_smc.h> 48 #include <kernel/tee_common_otp.h> 49 #include <mm/core_mmu.h> 50 51 static struct gic_data gic_data; 52 #ifdef CFG_PL011 53 static struct pl011_data console_data; 54 #else 55 static struct ns16550_data console_data; 56 #endif 57 58 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, 59 CORE_MMU_PGDIR_SIZE); 60 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 61 62 #if defined(PLATFORM_FLAVOR_lx2160ardb) 63 register_ddr(CFG_DRAM0_BASE, (CFG_TZDRAM_START - CFG_DRAM0_BASE)); 64 #ifdef CFG_DRAM1_BASE 65 register_ddr(CFG_DRAM1_BASE, CFG_DRAM1_SIZE); 66 #endif 67 #endif 68 69 #ifdef CFG_ARM32_core 70 void plat_primary_init_early(void) 71 { 72 vaddr_t addr; 73 74 #if defined(CFG_BOOT_SECONDARY_REQUEST) 75 /* set secondary entry address */ 76 io_write32(DCFG_BASE + DCFG_SCRATCHRW1, 77 __compiler_bswap32(TEE_LOAD_ADDR)); 78 79 /* release secondary cores */ 80 io_write32(DCFG_BASE + DCFG_CCSR_BRR /* cpu1 */, 81 __compiler_bswap32(0x1 << 1)); 82 dsb(); 83 sev(); 84 #endif 85 86 /* configure CSU */ 87 88 /* first grant all peripherals */ 89 for (addr = CSU_BASE + CSU_CSL_START; 90 addr != CSU_BASE + CSU_CSL_END; 91 addr += 4) 92 io_write32(addr, __compiler_bswap32(CSU_ACCESS_ALL)); 93 94 /* restrict key preipherals from NS */ 95 io_write32(CSU_BASE + CSU_CSL30, 96 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 97 io_write32(CSU_BASE + CSU_CSL37, 98 __compiler_bswap32(CSU_ACCESS_SEC_ONLY)); 99 100 /* lock the settings */ 101 for (addr = CSU_BASE + CSU_CSL_START; 102 addr != CSU_BASE + CSU_CSL_END; 103 addr += 4) 104 io_setbits32(addr, 105 __compiler_bswap32(CSU_SETTING_LOCK)); 106 } 107 #endif 108 109 void console_init(void) 110 { 111 #ifdef CFG_PL011 112 /* 113 * Everything for uart driver initialization is done in bootloader. 114 * So not reinitializing console. 115 */ 116 pl011_init(&console_data, CONSOLE_UART_BASE, 0, 0); 117 #else 118 ns16550_init(&console_data, CONSOLE_UART_BASE, IO_WIDTH_U8, 0); 119 #endif 120 register_serial_console(&console_data.chip); 121 } 122 123 void main_init_gic(void) 124 { 125 vaddr_t gicc_base; 126 vaddr_t gicd_base; 127 128 gicc_base = (vaddr_t)phys_to_virt(GIC_BASE + GICC_OFFSET, 129 MEM_AREA_IO_SEC); 130 gicd_base = (vaddr_t)phys_to_virt(GIC_BASE + GICD_OFFSET, 131 MEM_AREA_IO_SEC); 132 133 if (!gicc_base || !gicd_base) 134 panic(); 135 136 /* Initialize GIC */ 137 gic_init(&gic_data, gicc_base, gicd_base); 138 itr_init(&gic_data.chip); 139 } 140 141 void main_secondary_init_gic(void) 142 { 143 gic_cpu_init(&gic_data); 144 } 145 146 #ifdef CFG_HW_UNQ_KEY_REQUEST 147 148 #include <types_ext.h> 149 int get_hw_unique_key(uint64_t smc_func_id, uint64_t in_key, uint64_t size); 150 151 /* 152 * Issued when requesting to Secure Storage Key for secure storage. 153 * 154 * SiP Service Calls 155 * 156 * Register usage: 157 * r0/x0 SMC Function ID, OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 158 */ 159 #define OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY 0xFF14 160 #define OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY \ 161 OPTEE_SMC_CALL_VAL(OPTEE_SMC_32, OPTEE_SMC_FAST_CALL, \ 162 OPTEE_SMC_OWNER_SIP, \ 163 OPTEE_SMC_FUNCID_SIP_LS_HW_UNQ_KEY) 164 165 TEE_Result tee_otp_get_hw_unique_key(struct tee_hw_unique_key *hwkey) 166 { 167 TEE_Result res; 168 int ret = 0; 169 uint8_t hw_unq_key[sizeof(hwkey->data)] __aligned(64); 170 171 ret = get_hw_unique_key(OPTEE_SMC_FAST_CALL_SIP_LS_HW_UNQ_KEY, 172 virt_to_phys(hw_unq_key), sizeof(hwkey->data)); 173 174 if (ret < 0) { 175 EMSG("\nH/W Unique key is not fetched from the platform."); 176 res = TEE_ERROR_SECURITY; 177 } else { 178 memcpy(&hwkey->data[0], hw_unq_key, sizeof(hwkey->data)); 179 res = TEE_SUCCESS; 180 } 181 182 return res; 183 } 184 #endif 185