plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(

plat-vexpress: qemu_v8: support EL1 physical timer interrupt

Add support to configure the timer callout service based on interrupt
from the EL1 physical timer when configuration with SPMC at S-EL2
(CFG_CORE_SEL2_SPMC=y).

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: arm: support EL1 physical timer

When configured with an SPMC at S-EL2 (CFG_CORE_SEL2_SPMC=y) use the
(emulated) EL1 physical timer instead of the EL3 physical timer since
the latter then is us

core: arm: support EL1 physical timer

When configured with an SPMC at S-EL2 (CFG_CORE_SEL2_SPMC=y) use the
(emulated) EL1 physical timer instead of the EL3 physical timer since
the latter then is used by S-EL2.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: arm64.h: add {read,write}_cntp_{ct,tva,cva}l()

Add wrapper functions to read and write to the EL1 physical timer
registers cntp_ctl_el0, cntp_tval_el0, and cntp_cval_el0. These
registers are u

core: arm64.h: add {read,write}_cntp_{ct,tva,cva}l()

Add wrapper functions to read and write to the EL1 physical timer
registers cntp_ctl_el0, cntp_tval_el0, and cntp_cval_el0. These
registers are used when using the Arm Generic Timer with
CFG_CORE_SEL2_SPMC=y (Hafnium as SPMC at S-EL2).

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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plat-versal2: conf: Add maximum size of the DTB

The DTB size for the AMD platform is larger and does not fit into the
default size, leading to failure or panic at boot time due to size
issues.

Thus

plat-versal2: conf: Add maximum size of the DTB

The DTB size for the AMD platform is larger and does not fit into the
default size, leading to failure or panic at boot time due to size
issues.

Thus setting an explicit maximum size for the Device Tree Blob to
allow safe modifications. This ensures there is enough space when
appending or editing nodes/properties in the DTB.

Signed-off-by: Amey Avinash Raghatate <AmeyAvinash.Raghatate@amd.com>
Acked-by: Akshay Belsare <akshay.belsare@amd.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: fix hartid for primary hart when CFG_DYN_CONFIG=y

The hart ID is stored in s0 register not a0 register. This fixes
multi-hart boot hang issue.

Fixes: 29661368f51d ("core: riscv: preser

core: riscv: fix hartid for primary hart when CFG_DYN_CONFIG=y

The hart ID is stored in s0 register not a0 register. This fixes
multi-hart boot hang issue.

Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: fix hartid at secondary hart entry point

The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.

Fixes: 29661368f51d ("core: riscv: preserve hartid in

core: riscv: fix hartid at secondary hart entry point

The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.

Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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dts: stm32: add missing i2c1 and i2c2 instances in stm32mp131.dtsi

i2c1 and i2c2 instances were missing within the stm32mp131.dtsi file
hence add them to have complete description of the stm32mp131

dts: stm32: add missing i2c1 and i2c2 instances in stm32mp131.dtsi

i2c1 and i2c2 instances were missing within the stm32mp131.dtsi file
hence add them to have complete description of the stm32mp131 i2c
controllers.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: align DMA channel for QSPI in stm32mp151.dtsi

Fix indentation of DMA channel definition for QSPI node in
stm32mp151.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Re

dts: stm32: align DMA channel for QSPI in stm32mp151.dtsi

Fix indentation of DMA channel definition for QSPI node in
stm32mp151.dtsi.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas

plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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treewide: dts: stm32: remove deprecated pins-are-numbered in device tree

Align the binding and the stm32mp device tree with Linux kernel,
remove the deprecated properties pins-are-numbered.

No func

treewide: dts: stm32: remove deprecated pins-are-numbered in device tree

Align the binding and the stm32mp device tree with Linux kernel,
remove the deprecated properties pins-are-numbered.

No functional impact as it is not used in code.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
becau

clk: stm32mp25: force ARM_DIVSEL for flexgen63 config at 400MHz

When clkext2f is selected as the clock source, a division by 2
must be applied to the SSC register (A3x_SS_CHGCLKREQ.ARM_DIVSEL)
because the clkext2f frequency of 400MHz is not supported.

This patch also rename the function stm32mp2_a35_ss_on_hsi to
stm32mp2_a35_ss_on_bypass to be aligned with reference manual.

Fixes: 28c10f9efa6a ("clk: stm32mp25: Introduce STM32MP25 clocks platform")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: riscv: enable MMU earlier for secondary cores

Enable MMU for secondary harts earlier to ensure
proper access to symbols in ASLR virtual addresses.

Signed-off-by: Yu-Chien Peter Lin <peter.lin

core: riscv: enable MMU earlier for secondary cores

Enable MMU for secondary harts earlier to ensure
proper access to symbols in ASLR virtual addresses.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: allow enabling CFG_CORE_ASLR

Make ASLR configurable on RISC-V platforms.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

core: riscv: refactor MMU enablement code

Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identi

core: riscv: refactor MMU enablement code

Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identity mapped section to maintain
execution continuity during the VA->PA transition. It adjusts
the stack pointer, global pointer, thread pointer and ra register
with the ASLR offset.

The console is reinitialized after ASLR mapping is active since
the registered addresses need to be updated.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-develo

core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC

core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC-V calling convention, preserve
the hart ID in s0 (callee-saved) to avoid unnecessary
save-restore operations when making function calls.

Also, use temporary registers instead in set_tp, makes
it more consistent with set_sp.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), a

core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), and fallback to
platform-specific seed generation when Zkr is unavailable.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
ra

core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
randomly maps code and data in memory.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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riscv: add ELF header definitions

Add RISC-V specific ELF header definitions in a new header
file to support ELF parsing for handling dynamic relocations.

We referred to u-boot/arch/riscv/cpu/start

riscv: add ELF header definitions

Add RISC-V specific ELF header definitions in a new header
file to support ELF parsing for handling dynamic relocations.

We referred to u-boot/arch/riscv/cpu/start.S to obtain the
definitions we need in OP-TEE.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement ASLR base address calculation

Implement arch_aslr_base_addr() for RISC-V to compute the ASLR base
address using the provided seed.

The implementation maps addresses across th

core: riscv: implement ASLR base address calculation

Implement arch_aslr_base_addr() for RISC-V to compute the ASLR base
address using the provided seed.

The implementation maps addresses across the full virtual address space:
- When MSB of new based address is set, the address is mapped
to the upper half by extending MSB to 64-bit
- Otherwise, it's mapped to the lower half

This approach utilizes the entire available virtual address space for
ASLR (e.g. 512 GiB for Sv39).

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32: add tamper event detection configuration for stm32mp257f-ev1

Add and default enable support for the TAMP button present on the
stm32mp257f-ev1 board. It relies on the external tamper 1.

dts: stm32: add tamper event detection configuration for stm32mp257f-ev1

Add and default enable support for the TAMP button present on the
stm32mp257f-ev1 board. It relies on the external tamper 1.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp251.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides

dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp251.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides wakeup capabilities.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add tamper event detection configuration for stm32mp135f-dk

Add and default enable support for the TAMP button present on the
stm32mp135f-dk board. It relies on the external tamper 2.
Se

dts: stm32: add tamper event detection configuration for stm32mp135f-dk

Add and default enable support for the TAMP button present on the
stm32mp135f-dk board. It relies on the external tamper 2.
Set GPIOA6 as secure as it now serve this purpose.

Add and default disable support for a test setup of an active tamper
event detection that is feasible with the GPIO expansion present on the
stm32mp135f-dk board.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp131.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides

dts: stm32: use EXTI event instead of GIC SPI for TAMP in stm32mp131.dtsi

Rely on EXTI event for the tamper event detection instead of the GIC line.
The EXTI makes the link with the GIC and provides wakeup capabilities.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...