riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR

Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better
readability. Also, provide a function description.

Signed-off-by:

riscv: sbi_console: split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR

Split FID 0 from SBI_EXT_0_1_CONSOLE_PUTCHAR definition for better
readability. Also, provide a function description.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

riscv: sbi: minor cleanup for SBI HSM related definitions

Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated
type for function ID definition for better clarity and consistency
with th

riscv: sbi: minor cleanup for SBI HSM related definitions

Rename sbi_boot_hart() to sbi_hsm_hart_start() and use enumerated
type for function ID definition for better clarity and consistency
with the following commits.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://githu

core: riscv: Add semihosting.S for semihosting instructions

RISC-V architecture has defined the semihosting binary interface, which
consists of a special trap instruction sequence, in:
https://github.com/riscv-non-isa/riscv-semihosting

Add semihosting.S into RISC-V kernel folder to implement the trap
instruction sequence.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit

core: riscv: Fix PTE creation when freeing PTE

The core_mmu_pte_create() is also called when MM core frees the pages,
which means the PTE should be zero. Current implementation always sets
valid bit (V), which is not proper way when clearing PTE. Fix it by only
honoring pte_bits parameter, which may be constructed in
mattr_to_pte_bits().

The core_mmu_ptp_create() is used to create non-leaf PTE, which points
to the next level of the page table. According to RISC-V privilege Spec,
non-leaf PTE only needs V bit. Therefore, we just give the V bit to
core_mmu_pte_create() when we want to create non-leaf PTE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: riscv: Rename mattr_to_perms() to mattr_to_pte_bits()

This function not only constructs permission bits (R, W, X) of PTE, but
also other bits such as valid bit (V), user bit (U), global bit (G

core: riscv: Rename mattr_to_perms() to mattr_to_pte_bits()

This function not only constructs permission bits (R, W, X) of PTE, but
also other bits such as valid bit (V), user bit (U), global bit (G),
accessed bit (A), and dirty bit (D). Rename it to mattr_to_pte_bits()
for greater readability.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: riscv: Add .sbss and .sdata sections to linker script

Currently, the unclean .sbss section in RISC-V binary could be
problematic. This is because variables such as puts_lock may have
non-zero

core: riscv: Add .sbss and .sdata sections to linker script

Currently, the unclean .sbss section in RISC-V binary could be
problematic. This is because variables such as puts_lock may have
non-zero initial values, leading to failures in cpu_spin_trylock().
To address this issue, merge .sbss into .bss so that it is properly
cleared on boot. Both OpenSBI [1] and Linux [2] follow this approach.

Also, to benefit from global pointer relaxation, add .sdata after the
__global_pointer$ symbol.

Link: https://github.com/riscv-software-src/opensbi/blob/bb90a9ebf6d9a2fe7726978d594e82cdbaad7799/firmware/fw_base.ldS#L84 [1]
Link: https://github.com/torvalds/linux/blob/296455ade1fdcf5f8f8c033201633b60946c589a/include/asm-generic/vmlinux.lds.h#L1146 [2]
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

riscv: mm: Set A/D bits of PTE(page table entry) by default

According to RISC-V privileged ISA manual:
Each leaf PTE contains an accessed (A) and dirty (D) bit. The A bit
indicates the virtual page

riscv: mm: Set A/D bits of PTE(page table entry) by default

According to RISC-V privileged ISA manual:
Each leaf PTE contains an accessed (A) and dirty (D) bit. The A bit
indicates the virtual page has been read, written, or fetched from since
the last time the A bit was cleared. The D bit indicates the virtual
page has been written since the last time the D bit was cleared.
When a virtual page is accessed and the A bit is clear, or is written
and the D bit is clear, a page-fault exception is raised.

And the manual also suggests:
If the supervisor software does not rely on accessed and/or dirty bits,
it should always set them to 1 in the PTE to improve performance.

Since OP-TEE does not rely on A/D bits, we by default set them to 1 to
avoid unnecessary page-fault exceptions when OP-TEE touches those pages.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: riscv: Rename thread_return_to_ree() to thread_return_to_udomain()

The terminology "udomain", which means untrusted domain, is more precise
terminology for RISC-V architecture, where "domain"

core: riscv: Rename thread_return_to_ree() to thread_return_to_udomain()

The terminology "udomain", which means untrusted domain, is more precise
terminology for RISC-V architecture, where "domain" has already been
defined in RISC-V CoVE and Smmtt specifications.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: riscv: Include kernel/interrupt.h for thread_arch.c

Otherwise, the compiler can not find the declaration of
interrupt_main_handler().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-

core: riscv: Include kernel/interrupt.h for thread_arch.c

Otherwise, the compiler can not find the declaration of
interrupt_main_handler().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: Add missing initial value for read_tp()

The stack variable "tp" should have its initial value.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wikland

core: riscv: Add missing initial value for read_tp()

The stack variable "tp" should have its initial value.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and thread

riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and threads.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we

riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we
enable CFG_RISCV_SBI so that OP-TEE utilizes SBI to communicate with
other OS.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

show more ...

core: add new argument to init_external_dt()

Add argument to function init_external_dt() to allow callers to specify
the maximum size of external DTB to be initialized.

Signed-off-by: Raymond Mao <

core: add new argument to init_external_dt()

Add argument to function init_external_dt() to allow callers to specify
the maximum size of external DTB to be initialized.

Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

tree wide: CFG_INSECURE deprecates CFG_WARN_INSECURE

Replaces configuration switch CFG_WARN_INSECURE with CFG_INSECURE
The new name is better because the switch not only warns but also
change the OP

tree wide: CFG_INSECURE deprecates CFG_WARN_INSECURE

Replaces configuration switch CFG_WARN_INSECURE with CFG_INSECURE
The new name is better because the switch not only warns but also
change the OP-TEE core behavior as, for example, allowing absence
of secure storage rollback protection.

Suggested-by: Jérôme Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: riscv: Add support fault mitigations in non-threaded code

The previous commit
ce56605a0ede ("core: support fault mitigations in non-threaded code")
supports fault mitigations in non-threaded c

core: riscv: Add support fault mitigations in non-threaded code

The previous commit
ce56605a0ede ("core: support fault mitigations in non-threaded code")
supports fault mitigations in non-threaded code for ARM architecture.

This commit adds the related modification for RISC-V architecture to
support it too.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core: remove unused arguments from boot_init_primary_early()

Removes the now unused arguments from boot_init_primary_early().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by:

core: remove unused arguments from boot_init_primary_early()

Removes the now unused arguments from boot_init_primary_early().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Raymond Mao <raymond.mao@linaro.org>

show more ...

core: prefix header file guard names with __

Improves header files guard names consistency by using a __ prefix
where missing.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by:

core: prefix header file guard names with __

Improves header files guard names consistency by using a __ prefix
where missing.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: fix header file guard names

Fixes header file guards macro name prefix (mostly missing occurrences)
that should reflect the file base directory sub-path where applicable.

Reviewed-by: Jens Wi

core: fix header file guard names

Fixes header file guards macro name prefix (mostly missing occurrences)
that should reflect the file base directory sub-path where applicable.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

core: riscv: Fix logic of thread_{get/set}_exceptions()

In ARM, the bits in DAIF register are used to mask the interrupts. While
in RISC-V, the bits in CSR XIE are used to enable(unmask) correspondi

core: riscv: Fix logic of thread_{get/set}_exceptions()

In ARM, the bits in DAIF register are used to mask the interrupts. While
in RISC-V, the bits in CSR XIE are used to enable(unmask) corresponding
interrupt sources.

To not modify the function of thread_get_exceptions(), we invert the
bits after reading the value of CSR XIE, as mask.

To not modify the function of thread_set_exceptions(), we invert the
bits in given "exceptions" before writing "exceptions" into CSR
XIE. Therefore, the intended masked exception bits will be cleared
when we write the final value into CSR XIE to mask those interrupts.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: Register thread_vector_table in primary CPU initialization

When primary CPU has initialized everything, it registers the address
of thread_vector_table into higher privileged software v

core: riscv: Register thread_vector_table in primary CPU initialization

When primary CPU has initialized everything, it registers the address
of thread_vector_table into higher privileged software via a1 register.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: Implement thread_vector_table for ABI and FIQ entries

Implement thread_vector_table which only includes entries for standard
ABI, fast ABI, and foreign interrupts. Most of code is refer

core: riscv: Implement thread_vector_table for ABI and FIQ entries

Implement thread_vector_table which only includes entries for standard
ABI, fast ABI, and foreign interrupts. Most of code is referenced from
ARM architecture. The thread_vector_table will be registered into higher
privileged software, such as M-mode firmware. The higher privileged
software can jump(mret) to OP-TEE based on this vector table.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: Implement SBI based protocol

Rename thread_return_from_nsec_call() to thread_return_to_ree() for more
general behavior, since TEE might not only be called by REE, but also
do something

core: riscv: Implement SBI based protocol

Rename thread_return_from_nsec_call() to thread_return_to_ree() for more
general behavior, since TEE might not only be called by REE, but also
do something on its own initiative (e.g., handle secure interrupts).

This commit also implements SBI based protocol used to return control to
REE. The register a7 encodes SBI TEE extension ID, which is temporarily
defined here. We may have ratified SBI TEE extension in the future and
we can apply ratified ID at that time. The register a6 is unused and
encoded as 0. The returned arguments are encoded into registers a0~a5
and should be provided by the caller.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: riscv: Implement panic_at_abi_return as guard of ABI call

The ABI call to REE domain should not return. We implement
panic_at_abi_return macro as guard of ABI call. When the ABI call return
il

core: riscv: Implement panic_at_abi_return as guard of ABI call

The ABI call to REE domain should not return. We implement
panic_at_abi_return macro as guard of ABI call. When the ABI call return
illegally, the system will enter panic or an infinite loop.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...