core: riscv: core_mmu_arch: zero-initialize new page tables

New page table pages must always start cleared. On some
platforms (e.g., QEMU) RAM happens to be zeroed at reset,
but on real hardware (FP

core: riscv: core_mmu_arch: zero-initialize new page tables

New page table pages must always start cleared. On some
platforms (e.g., QEMU) RAM happens to be zeroed at reset,
but on real hardware (FPGA/SoC DDR) may not be the case.
Without this memset, stale contents can make
core_mmu_map_region() see non-zero old_attr and panic with
"Page is already mapped" when CFG_DYN_CONFIG is enabled.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: kernel: simplify hartid query API

The thread_get_hartid_by_hartindex() function is removed as there
is no need to query remote hartids. Additionally, using this API
before secondary har

core: riscv: kernel: simplify hartid query API

The thread_get_hartid_by_hartindex() function is removed as there
is no need to query remote hartids. Additionally, using this API
before secondary hart initialization would return incorrect values.

Replace with the simpler thread_get_hartid() which returns the current
hart's ID reliably.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: kernel: add hart index sanity check

Add debug-only bounds checking in __get_core_pos() to prevent
out-of-bounds array access into per-core data structures.

Signed-off-by: Yu-Chien Pete

core: riscv: kernel: add hart index sanity check

Add debug-only bounds checking in __get_core_pos() to prevent
out-of-bounds array access into per-core data structures.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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ftrace: dump ftrace after every ta_entry

This patch implements the feature to dump ftrace buffer to
tee_supplicant after every entry to the ta.
To implement the feature, this patch does some modific

ftrace: dump ftrace after every ta_entry

This patch implements the feature to dump ftrace buffer to
tee_supplicant after every entry to the ta.
To implement the feature, this patch does some modification to the
ftrace dumping process and add a new config CFG_FTRACE_DUMP_EVERY_ENTRY
to control this behavior.
This can reduce the chance of losing the ftrace data due to not
enough ftrace buffer and make debugging long-lived TA possible.

Signed-off-by: Leo Chen <shf.chen@mediatek.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shi

core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shift byte for differ environmnt. therefore remove the const value and
using REGOFF() macro to fit the RV32/RV64 environment.

Signed-off-by: Randolph Lin <randolph@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: add build config for MPXY/RPMI support

Enable compilation of MPXY/RPMI support by introducing the build
option `CFG_RISCV_SBI_MPXY_RPMI`.

This commit:
- Adds sbi_mpxy_rpmi.c to the bui

core: riscv: add build config for MPXY/RPMI support

Enable compilation of MPXY/RPMI support by introducing the build
option `CFG_RISCV_SBI_MPXY_RPMI`.

This commit:
- Adds sbi_mpxy_rpmi.c to the build when the option is enabled
- Forces `CFG_RISCV_SBI_MPXY` when MPXY/RPMI is selected
- Enables CFG_RISCV_SBI_MPXY_RPMI in plat-virt by default

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: add initial RPMI/MPXY integration support

This commit introduces infrastructure to support RPMI communication via
the SBI MPXY extension. MPXY allows supervisor software to send and
rec

core: riscv: add initial RPMI/MPXY integration support

This commit introduces infrastructure to support RPMI communication via
the SBI MPXY extension. MPXY allows supervisor software to send and
receive RPMI messages through M-mode firmware acting as a proxy.

Functions added by this commit are sufficient to implement the
RequestForward service group.

Support for asynchronous events, notifications, and MSI-based message
delivery will be added in future commits.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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riscv: sbi_mpxy_rpmi.h: add RPMI protocol-specific definitions for MPXY

Introduce sbi_mpxy_rpmi.h, a header defining RPMI message protocol
attributes and message types specific to the MPXY SBI exten

riscv: sbi_mpxy_rpmi.h: add RPMI protocol-specific definitions for MPXY

Introduce sbi_mpxy_rpmi.h, a header defining RPMI message protocol
attributes and message types specific to the MPXY SBI extension.
This includes enums for attribute and message type identifiers, a
unified RPMI message structure, and helper initializers to simplify
message construction.

These definitions serve as the interface between supervisor-level RPMI
clients and the underlying MPXY transport.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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riscv: rpmi.h: add defines of RISC-V RPMI messaging protocol

The RPMI messaging protocol includes all the RPMI messages exchanged
over a RPMI transport channel.

*NOTE*: The RISC-V RPMI specificatio

riscv: rpmi.h: add defines of RISC-V RPMI messaging protocol

The RPMI messaging protocol includes all the RPMI messages exchanged
over a RPMI transport channel.

*NOTE*: The RISC-V RPMI specification is not yet ratified
as a full standard. This is based on the v0.99 draft released during
May–June 2025 The draft is frozen and in public review.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: introduce CFG_RISCV_SBI_MPXY flag for MPXY SBI support

Add a new build-time configuration flag CFG_RISCV_SBI_MPXY to enable
compilation of MPXY SBI extension support in OP-TEE. When ena

core: riscv: introduce CFG_RISCV_SBI_MPXY flag for MPXY SBI support

Add a new build-time configuration flag CFG_RISCV_SBI_MPXY to enable
compilation of MPXY SBI extension support in OP-TEE. When enabled, this
automatically forces CFG_RISCV_SBI to ensure the SBI infrastructure is
included.

Also update the build system to conditionally compile sbi_mpxy.c based
on this flag.

Enable CFG_RISCV_SBI_MPXY by default for the virt platform.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement MPXY SBI extension

Introduce support for the MPXY SBI extension (EID #0x4D505859),
which enables supervisor software to exchange messages through
an abstract SBI interface dec

core: riscv: implement MPXY SBI extension

Introduce support for the MPXY SBI extension (EID #0x4D505859),
which enables supervisor software to exchange messages through
an abstract SBI interface decoupled from any specific protocol.

MPXY allows setting up per-hart shared memory for transferring
messages between the supervisor and an SBI implementation.
It serves as a generic backend to build messaging clients,
while being agnostic of message protocol semantics.

This step provides the foundation for future inter-domain
message exchange.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: include: misc_arch.h: include stdint.h for uint32_t type

Added <stdint.h> to ensure types like uint32_t are correctly defined,
resolving implicit type issues when including this header.

core: riscv: include: misc_arch.h: include stdint.h for uint32_t type

Added <stdint.h> to ensure types like uint32_t are correctly defined,
resolving implicit type issues when including this header.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: sbi.h: expose sbi_ecall helper in public header

Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across
individual SBI extension implementations. This prepares for modular

core: riscv: sbi.h: expose sbi_ecall helper in public header

Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across
individual SBI extension implementations. This prepares for modularizing
each SBI extension (e.g., HSM, MPXY) into its own file while
centralizing the ecall interface.

Removes the now-duplicated inline definition from sbi.c.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: sbi.h: add SBI_EXT_MPXY definition

Added `SBI_EXT_MPXY` (0x4D505859) as per latest RISC-V SBI extensions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvi

core: riscv: sbi.h: add SBI_EXT_MPXY definition

Added `SBI_EXT_MPXY` (0x4D505859) as per latest RISC-V SBI extensions.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: sbi.h: extend SBI error codes

Add more SBI error codes to synchronize with SBI specification.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alv

core: riscv: sbi.h: extend SBI error codes

Add more SBI error codes to synchronize with SBI specification.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: fix hartid for primary hart when CFG_DYN_CONFIG=y

The hart ID is stored in s0 register not a0 register. This fixes
multi-hart boot hang issue.

Fixes: 29661368f51d ("core: riscv: preser

core: riscv: fix hartid for primary hart when CFG_DYN_CONFIG=y

The hart ID is stored in s0 register not a0 register. This fixes
multi-hart boot hang issue.

Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: fix hartid at secondary hart entry point

The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.

Fixes: 29661368f51d ("core: riscv: preserve hartid in

core: riscv: fix hartid at secondary hart entry point

The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.

Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: enable MMU earlier for secondary cores

Enable MMU for secondary harts earlier to ensure
proper access to symbols in ASLR virtual addresses.

Signed-off-by: Yu-Chien Peter Lin <peter.lin

core: riscv: enable MMU earlier for secondary cores

Enable MMU for secondary harts earlier to ensure
proper access to symbols in ASLR virtual addresses.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: allow enabling CFG_CORE_ASLR

Make ASLR configurable on RISC-V platforms.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

core: riscv: refactor MMU enablement code

Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identi

core: riscv: refactor MMU enablement code

Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identity mapped section to maintain
execution continuity during the VA->PA transition. It adjusts
the stack pointer, global pointer, thread pointer and ra register
with the ASLR offset.

The console is reinitialized after ASLR mapping is active since
the registered addresses need to be updated.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-develo

core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC

core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC-V calling convention, preserve
the hart ID in s0 (callee-saved) to avoid unnecessary
save-restore operations when making function calls.

Also, use temporary registers instead in set_tp, makes
it more consistent with set_sp.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), a

core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), and fallback to
platform-specific seed generation when Zkr is unavailable.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
ra

core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
randomly maps code and data in memory.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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