core: riscv: add build config for MPXY/RPMI support

Enable compilation of MPXY/RPMI support by introducing the build
option `CFG_RISCV_SBI_MPXY_RPMI`.

This commit:
- Adds sbi_mpxy_rpmi.c to the bui

core: riscv: add build config for MPXY/RPMI support

Enable compilation of MPXY/RPMI support by introducing the build
option `CFG_RISCV_SBI_MPXY_RPMI`.

This commit:
- Adds sbi_mpxy_rpmi.c to the build when the option is enabled
- Forces `CFG_RISCV_SBI_MPXY` when MPXY/RPMI is selected
- Enables CFG_RISCV_SBI_MPXY_RPMI in plat-virt by default

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: introduce CFG_RISCV_SBI_MPXY flag for MPXY SBI support

Add a new build-time configuration flag CFG_RISCV_SBI_MPXY to enable
compilation of MPXY SBI extension support in OP-TEE. When ena

core: riscv: introduce CFG_RISCV_SBI_MPXY flag for MPXY SBI support

Add a new build-time configuration flag CFG_RISCV_SBI_MPXY to enable
compilation of MPXY SBI extension support in OP-TEE. When enabled, this
automatically forces CFG_RISCV_SBI to ensure the SBI infrastructure is
included.

Also update the build system to conditionally compile sbi_mpxy.c based
on this flag.

Enable CFG_RISCV_SBI_MPXY by default for the virt platform.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: allow enabling CFG_CORE_ASLR

Make ASLR configurable on RISC-V platforms.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

core: riscv: allow enabling CFG_WITH_STACK_CANARIES

Remove force disablement of randomized stack canary for OP-TEE core.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin

core: riscv: allow enabling CFG_WITH_STACK_CANARIES

Remove force disablement of randomized stack canary for OP-TEE core.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>

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riscv: plat-virt: move stack alignment definition

The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configurat

riscv: plat-virt: move stack alignment definition

The 16-byte stack alignment is a RISC-V ABI requirement
that applies to all RISC-V platforms. Move this definition
from the virt platform configuration to riscv.h.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: plat-virt: add APLIC and IMSIC support for QEMU virt platform

- Add APLIC and IMSIC configurations for the QEMU virt platform.
- Override the interrupt controller initialization and interrupt

riscv: plat-virt: add APLIC and IMSIC support for QEMU virt platform

- Add APLIC and IMSIC configurations for the QEMU virt platform.
- Override the interrupt controller initialization and interrupt handler
functions when using APLIC or IMSIC.

Signed-off-by: Huang Borong <huangborong@bosc.ac.cn>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: plat-virt: Let console devices be build time configurable

Currently RISC-V virtual platform enforces 16550 UART to be console
device. However, there are other console devices which can be cho

riscv: plat-virt: Let console devices be build time configurable

Currently RISC-V virtual platform enforces 16550 UART to be console
device. However, there are other console devices which can be chose by
developer. Thus, we allow the configurations for console device to be
overridden at build time while keeping the default value enabled.

Besides, fix CFG_SBI_CONSOLE to be CFG_RISCV_SBI_CONSOLE.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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riscv: plat-virt: Let CFG_RISCV_PLIC be build time configurable

RISC-V has several standard interrupt controllers supported by QEMU
virtual platform. Thus, we allow CFG_RISCV_PLIC to be overridden a

riscv: plat-virt: Let CFG_RISCV_PLIC be build time configurable

RISC-V has several standard interrupt controllers supported by QEMU
virtual platform. Thus, we allow CFG_RISCV_PLIC to be overridden at
build time while keeping the default value enabled.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: plat-virt: allow enabling CFG_TEE_CORE_DEBUG for virt machine

Allow enabling CFG_TEE_CORE_DEBUG to make assertions useful.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed

riscv: plat-virt: allow enabling CFG_TEE_CORE_DEBUG for virt machine

Allow enabling CFG_TEE_CORE_DEBUG to make assertions useful.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: Let platform choose native and foreign interrupts

Platform may want to choose different types of native and foreign
interrupts. This commit adds two definitions for the platforms:
1. PL

core: riscv: Let platform choose native and foreign interrupts

Platform may want to choose different types of native and foreign
interrupts. This commit adds two definitions for the platforms:
1. PLAT_THREAD_EXCP_FOREIGN_INTR: to define platform specific foreign
interrupts
2. PLAT_THREAD_EXCP_NATIVE_INTR: to define platform specific native
interrupts.

For RISC-V virt machine, we define all external/mtimer/software
interrupts as foreign interrupts. For RISC-V spike platform, we define
external interrupts as foreign interrupts, and mtimer/software
interrupts as native interrupts.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: Set CFG_BOOT_SYNC_CPU=n

On RISC-V QEMU virt platform, OP-TEE OS runs as S-mode. There is a
secure monitor runs as M-mode and controls the hart state of the
secondary CPUs in SMP sy

riscv: plat-virt: Set CFG_BOOT_SYNC_CPU=n

On RISC-V QEMU virt platform, OP-TEE OS runs as S-mode. There is a
secure monitor runs as M-mode and controls the hart state of the
secondary CPUs in SMP system (e.g., by SBI HSM extension) during OP-TEE
OS secondary CPUs booting.

Thus, RISC-V virt platform does not need CFG_BOOT_SYNC_CPU.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, ena

core: riscv: use configuration options for RISC-V extensions

RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".

Also, enable RVC and FPU extension for QEMU virt machine.

Note that the RISC-V FPU for OP-TEE will be introduced later.
Enable FPU to temporarily bypass incompatible soft/hard-fp
linker errors.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: switch to dynamic shared memory

Enable dynamic shared memory for QEMU virt machine.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@an

riscv: plat-virt: switch to dynamic shared memory

Enable dynamic shared memory for QEMU virt machine.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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riscv: plat-virt: Enable CFG_HWRNG_PTA

Enable CFG_HWRNG_PTA with the implementation of the RISC-V
Zkr driver which provides the hardware entropy source.

Signed-off-by: Alvin Chang <alvinga@andestec

riscv: plat-virt: Enable CFG_HWRNG_PTA

Enable CFG_HWRNG_PTA with the implementation of the RISC-V
Zkr driver which provides the hardware entropy source.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: plat-virt: Set CFG_RISCV_WITH_M_MODE_SM as 'y'

In RISC-V QEMU virtual platform, OP-TEE OS uses M-mode secure monitor
based solution to communicate with the untrusted domain. Therefore, set
CF

riscv: plat-virt: Set CFG_RISCV_WITH_M_MODE_SM as 'y'

In RISC-V QEMU virtual platform, OP-TEE OS uses M-mode secure monitor
based solution to communicate with the untrusted domain. Therefore, set
CFG_RISCV_WITH_M_MODE_SM to 'y' in its configuration file.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

riscv: virt: Enable CFG_DT

Enable CFG_DT to parse the external DTB passed by previous boot stage.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and thread

riscv: virt: Relax the configurations related to hart/thread number

Do not force the CFG_TEE_CORE_NB_CORE and CFG_NUM_THREADS to be 1, since
we may run SMP system which has multiple harts and threads.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we

riscv: virt: Enable configurations for S-mode execution

In RISC-V QEMU virtual platform, we run OP-TEE as S-mode. This commit
forcely enables CFG_RISCV_S_MODE and disables CFG_RISCV_M_MODE. Also, we
enable CFG_RISCV_SBI so that OP-TEE utilizes SBI to communicate with
other OS.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x6

riscv: plat-virt: Align PLIC configurations with QEMU v8.1.1

Align the PLIC configurations with RISC-V QEMU virtual platform based on
official QEMU v8.1.1 tag. The maximum size of PLIC should be 0x600000,
and the number of interrupt sources should be 95.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
f

drivers: plic: Maintain controller data in driver source file

To align the design from other architecture, we move the interrupt
controller data instance from platform source file to driver source
file. With this change, the PLIC initialization functions no more get
the controller data as input argument. Platforms do not need to care
about the interrupt controller data instance.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
inclu

riscv: plat-virt: Rename to latest interrupt controller functions

Rename main_init_plic() to boot_primary_init_intc(). Rename
main_secondary_init_plic() to boot_secondary_init_intc(). Also the
include path of RISC-V PLIC driver header is fixed.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: fix interrupt_main_handler() reference

Fixes itr_core_handler() reference in RiscV architecture that was renamed
interrupt_main_handler() in commit referred below.

Fixes: 358bf47c0612

core: riscv: fix interrupt_main_handler() reference

Fixes itr_core_handler() reference in RiscV architecture that was renamed
interrupt_main_handler() in commit referred below.

Fixes: 358bf47c0612 ("core: interrupt: rename itr_core_handler()")
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain s

riscv: plat-virt: Override default platform ISA extensions

RV64 virtual platform on QEMU supports C(compressed), Zicsr, and
Zifencei extensions. To specify the ISA extensions into RISC-V
toolchain so that toolchain can generate the code correctly, these
ISA extensions should be encoded into "-march" flag. This patch
overrides the default ISA extensions which is defined in riscv.mk
to specify the extension that the platform really supports.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <je

core: interrupt: rename itr_init()

Renames itr_init() to interrupt_main_init() as a later
change will modify interrupt chip API functions using interrupt_
as prefix.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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