core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shi

core: riscv: spinlock.S: use REGOFF for stack push and pop

In __cpu_spin_lock(), using STR/LDR and RISCV_XLEN_BYTES, it seems
that it wants to adopt the RV64 or RV32 environment, but missing the
shift byte for differ environmnt. therefore remove the const value and
using REGOFF() macro to fit the RV32/RV64 environment.

Signed-off-by: Randolph Lin <randolph@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>

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core: riscv: add build config for MPXY/RPMI support

Enable compilation of MPXY/RPMI support by introducing the build
option `CFG_RISCV_SBI_MPXY_RPMI`.

This commit:
- Adds sbi_mpxy_rpmi.c to the bui

core: riscv: add build config for MPXY/RPMI support

Enable compilation of MPXY/RPMI support by introducing the build
option `CFG_RISCV_SBI_MPXY_RPMI`.

This commit:
- Adds sbi_mpxy_rpmi.c to the build when the option is enabled
- Forces `CFG_RISCV_SBI_MPXY` when MPXY/RPMI is selected
- Enables CFG_RISCV_SBI_MPXY_RPMI in plat-virt by default

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: add initial RPMI/MPXY integration support

This commit introduces infrastructure to support RPMI communication via
the SBI MPXY extension. MPXY allows supervisor software to send and
rec

core: riscv: add initial RPMI/MPXY integration support

This commit introduces infrastructure to support RPMI communication via
the SBI MPXY extension. MPXY allows supervisor software to send and
receive RPMI messages through M-mode firmware acting as a proxy.

Functions added by this commit are sufficient to implement the
RequestForward service group.

Support for asynchronous events, notifications, and MSI-based message
delivery will be added in future commits.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: introduce CFG_RISCV_SBI_MPXY flag for MPXY SBI support

Add a new build-time configuration flag CFG_RISCV_SBI_MPXY to enable
compilation of MPXY SBI extension support in OP-TEE. When ena

core: riscv: introduce CFG_RISCV_SBI_MPXY flag for MPXY SBI support

Add a new build-time configuration flag CFG_RISCV_SBI_MPXY to enable
compilation of MPXY SBI extension support in OP-TEE. When enabled, this
automatically forces CFG_RISCV_SBI to ensure the SBI infrastructure is
included.

Also update the build system to conditionally compile sbi_mpxy.c based
on this flag.

Enable CFG_RISCV_SBI_MPXY by default for the virt platform.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement MPXY SBI extension

Introduce support for the MPXY SBI extension (EID #0x4D505859),
which enables supervisor software to exchange messages through
an abstract SBI interface dec

core: riscv: implement MPXY SBI extension

Introduce support for the MPXY SBI extension (EID #0x4D505859),
which enables supervisor software to exchange messages through
an abstract SBI interface decoupled from any specific protocol.

MPXY allows setting up per-hart shared memory for transferring
messages between the supervisor and an SBI implementation.
It serves as a generic backend to build messaging clients,
while being agnostic of message protocol semantics.

This step provides the foundation for future inter-domain
message exchange.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: sbi.h: expose sbi_ecall helper in public header

Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across
individual SBI extension implementations. This prepares for modular

core: riscv: sbi.h: expose sbi_ecall helper in public header

Move `sbi_ecall()` and `struct sbiret` to sbi.h to allow reuse across
individual SBI extension implementations. This prepares for modularizing
each SBI extension (e.g., HSM, MPXY) into its own file while
centralizing the ecall interface.

Removes the now-duplicated inline definition from sbi.c.

Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: fix hartid for primary hart when CFG_DYN_CONFIG=y

The hart ID is stored in s0 register not a0 register. This fixes
multi-hart boot hang issue.

Fixes: 29661368f51d ("core: riscv: preser

core: riscv: fix hartid for primary hart when CFG_DYN_CONFIG=y

The hart ID is stored in s0 register not a0 register. This fixes
multi-hart boot hang issue.

Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: fix hartid at secondary hart entry point

The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.

Fixes: 29661368f51d ("core: riscv: preserve hartid in

core: riscv: fix hartid at secondary hart entry point

The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.

Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: enable MMU earlier for secondary cores

Enable MMU for secondary harts earlier to ensure
proper access to symbols in ASLR virtual addresses.

Signed-off-by: Yu-Chien Peter Lin <peter.lin

core: riscv: enable MMU earlier for secondary cores

Enable MMU for secondary harts earlier to ensure
proper access to symbols in ASLR virtual addresses.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: refactor MMU enablement code

Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identi

core: riscv: refactor MMU enablement code

Replace the set_satp macro with a proper enable_mmu function
to handle the transition to randomized virtual addresses. The
function executes from the identity mapped section to maintain
execution continuity during the VA->PA transition. It adjusts
the stack pointer, global pointer, thread pointer and ra register
with the ASLR offset.

The console is reinitialized after ASLR mapping is active since
the registered addresses need to be updated.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-develo

core: riscv: add RISC-V relocation handling

Process relocations during boot to adjust addresses
with randomized offset at runtime.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC

core: riscv: preserve hartid in s0 register at entry point

The hartid is initially passed in a0 register. Since we
will introduce function calls in subsequent patches and
a0 is caller-saved per RISC-V calling convention, preserve
the hart ID in s0 (callee-saved) to avoid unnecessary
save-restore operations when making function calls.

Also, use temporary registers instead in set_tp, makes
it more consistent with set_sp.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), a

core: riscv: implement get_aslr_seed() function

Implement the get_aslr_seed() function to provide ASLR
seed generation. Prefer sourcing the seed through the
hardware RNG (using the Zkr extension), and fallback to
platform-specific seed generation when Zkr is unavailable.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
ra

core: riscv: kern.ld.S: add relocation sections for ASLR

Add .rela.dyn and .data.rel.ro sections to support position-independent
code. These sections store the relocation entries needed when ASLR
randomly maps code and data in memory.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

core: riscv: make boot_mmu_config global and add it into identity_map

Change boot_mmu_config from LOCAL_DATA to DATA to make
it globally accessible. Also, add it into data section
of identity_map.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: replace CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG

This commit replaces CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG since now
RISC-V also supports CFG_DYN_STACK_CONFIG.

Signed-off-by: Alvin Chang

core: replace CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG

This commit replaces CFG_DYN_STACK_CONFIG with CFG_DYN_CONFIG since now
RISC-V also supports CFG_DYN_STACK_CONFIG.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: dynamic allocation of thread_core_local and its stacks

Refer to commit 59724f223500 ("core: dynamic allocation of
thread_core_local and its stacks"), we implement the code for RISC-V
ar

core: riscv: dynamic allocation of thread_core_local and its stacks

Refer to commit 59724f223500 ("core: dynamic allocation of
thread_core_local and its stacks"), we implement the code for RISC-V
architecture. With CFG_DYN_STACK_CONFIG enabled, the thread_core_local
and the two stacks, tmp_stack and abt_stack, are dynamically allocated.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: riscv: Call page_alloc_init()

Call page_alloc_init() from init_primary() after unused boot memory has
been released.

This commit is to synchronize the boot stages with ARM architecture,
intro

core: riscv: Call page_alloc_init()

Call page_alloc_init() from init_primary() after unused boot memory has
been released.

This commit is to synchronize the boot stages with ARM architecture,
introduced in commit 0e12fb0c2d75 ("core: arm: boot: call
page_alloc_init()") and commit 3e7d042b5d1e ("core: arm: boot: fix
calling page_alloc_init()").

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: Refactor boot

Move initialization of thread_core_local[] from very early to
boot_init_primary_late() and introduce boot_init_primary_runtime().

This commit is to synchronize the boot s

core: riscv: Refactor boot

Move initialization of thread_core_local[] from very early to
boot_init_primary_late() and introduce boot_init_primary_runtime().

This commit is to synchronize the boot stages with ARM architecture,
introduced in commit b5ec8152f3e5 ("core: arm: refactor boot") and
commit b0da0d592ac4 ("core: boot: add boot_init_primary_runtime()").

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: riscv: Remove init_sec_mon()

In RISC-V architecture, the secure monitor is always initialized before
jumping into OP-TEE. Thus, init_sec_mon() can be deprecated.

Signed-off-by: Alvin Chang <a

core: riscv: Remove init_sec_mon()

In RISC-V architecture, the secure monitor is always initialized before
jumping into OP-TEE. Thus, init_sec_mon() can be deprecated.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>

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core: add thread_count to thread_init_threads()

Add a thread_count parameter to thread_init_threads(). This must currently
always be equal to CFG_NUM_THREADS, but may become a dynamic configuration

core: add thread_count to thread_init_threads()

Add a thread_count parameter to thread_init_threads(). This must currently
always be equal to CFG_NUM_THREADS, but may become a dynamic configuration
parameter with CFG_DYN_CONFIG=y in later patches.

The array threads[] is changed into a pointer to allow dynamic
allocation in later patches. The assembly code is updated accordingly to
handle a pointer instead of an array.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Tested-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add core_count to thread_init_thread_core_local()

Add a core_count parameter to thread_init_thread_core_local() to enable
dynamic configuration of the number of supported cores when configured

core: add core_count to thread_init_thread_core_local()

Add a core_count parameter to thread_init_thread_core_local() to enable
dynamic configuration of the number of supported cores when configured
with CFG_DYN_STACK_CONFIG=y, or it must be equal to
CFG_TEE_CORE_NB_CORE. This is needed in later patches where the number
of cores is configured dynamically.

The array thread_core_local[] is changed into a pointer to allow dynamic
allocation in later patches. The assembly code is updated accordingly to
handle a pointer instead of an array.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: riscv: support random stack canaries for stack protector

Call plat_get_random_stack_canaries() and update the value of
__stack_chk_guard during early initialization, so that the
random stack c

core: riscv: support random stack canaries for stack protector

Call plat_get_random_stack_canaries() and update the value of
__stack_chk_guard during early initialization, so that the
random stack canaries can be used to detect stack overflow
and buffer overflow.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Co-developed-by: Alvin Chang <alvinga@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>

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tree wide: fix header files dependencies in linker files

When linking with a generated linker script like kern.ld.S, dependencies
with header file are not regenerated.
Same issue as
commit acdc32afe

tree wide: fix header files dependencies in linker files

When linking with a generated linker script like kern.ld.S, dependencies
with header file are not regenerated.
Same issue as
commit acdc32afe18f ("mk/compile.mk: fix header dependency in .d file")

Add option -MP used to fix error generated when removing header files.

Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: kernel: support booting non-contiguous non-zero-based hart IDs

Currently, OP-TEE assumes 0 <= hartid < CFG_TEE_CORE_NB_CORE,
and must be contiguous, which fails to accommodate different
CPU t

riscv: kernel: support booting non-contiguous non-zero-based hart IDs

Currently, OP-TEE assumes 0 <= hartid < CFG_TEE_CORE_NB_CORE,
and must be contiguous, which fails to accommodate different
CPU topologies. For example, some RISC-V platforms, such as
the HiFive Unmatched board, do not run Linux and OP-TEE on
hart0, as it is a monitor core without supervisor mode support.

To address this, introduce hart_index, which is used to index
per-hart structures, such as thread_core_local and root_pgt.
The hart_index will range from 0 to (CFG_TEE_CORE_NB_CORE - 1),
and the primary hart will have an index of 0.

Additionally, a new function, boot_primary_init_core_ids(),
is added to initialize secondary hart IDs for booting via
sbi_hsm_hart_start().

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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