1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2023 Andes Technology Corporation 4 * Copyright 2022-2023 NXP 5 */ 6 7 #include <assert.h> 8 #include <compiler.h> 9 #include <config.h> 10 #include <console.h> 11 #include <keep.h> 12 #include <kernel/boot.h> 13 #include <kernel/dt.h> 14 #include <kernel/linker.h> 15 #include <kernel/misc.h> 16 #include <kernel/panic.h> 17 #include <kernel/thread.h> 18 #include <libfdt.h> 19 #include <mm/core_memprot.h> 20 #include <mm/core_mmu.h> 21 #include <mm/tee_mm.h> 22 #include <mm/tee_pager.h> 23 #include <platform_config.h> 24 #include <riscv.h> 25 #include <sbi.h> 26 #include <stdio.h> 27 #include <trace.h> 28 #include <util.h> 29 30 #define PADDR_INVALID ULONG_MAX 31 32 paddr_t start_addr; 33 34 uint32_t sem_cpu_sync[CFG_TEE_CORE_NB_CORE]; 35 uint32_t hartids[CFG_TEE_CORE_NB_CORE]; 36 37 #if defined(CFG_DT) 38 static int mark_tddram_as_reserved(struct dt_descriptor *dt) 39 { 40 return add_res_mem_dt_node(dt, "optee_core", CFG_TDDRAM_START, 41 CFG_TDDRAM_SIZE); 42 } 43 44 static void update_external_dt(void) 45 { 46 struct dt_descriptor *dt = get_external_dt_desc(); 47 48 if (!dt || !dt->blob) 49 return; 50 51 #ifdef CFG_CORE_RESERVED_SHM 52 if (mark_static_shm_as_reserved(dt)) 53 panic("Failed to config non-secure memory"); 54 #endif 55 56 if (mark_tddram_as_reserved(dt)) 57 panic("Failed to config secure memory"); 58 } 59 #else /*CFG_DT*/ 60 static void update_external_dt(void) 61 { 62 } 63 #endif /*!CFG_DT*/ 64 65 #ifdef CFG_RISCV_S_MODE 66 static void start_secondary_cores(void) 67 { 68 uint32_t curr_hartid = thread_get_core_local()->hart_id; 69 enum sbi_hsm_hart_state status = 0; 70 uint32_t hartid = 0; 71 int rc = 0; 72 int i = 0; 73 74 /* The primary CPU is always indexed by 0 */ 75 assert(get_core_pos() == 0); 76 77 for (i = 0; i < CFG_TEE_CORE_NB_CORE; i++) { 78 hartid = hartids[i]; 79 80 if (hartid == curr_hartid) 81 continue; 82 83 rc = sbi_hsm_hart_get_status(hartid, &status); 84 /* 85 * Skip if the hartid is not an assigned hart 86 * of the trusted domain, or its HSM state is 87 * not stopped. 88 */ 89 if (rc || status != SBI_HSM_STATE_STOPPED) 90 continue; 91 92 DMSG("Bringing up secondary hart%"PRIu32, hartid); 93 94 rc = sbi_hsm_hart_start(hartid, start_addr, 0 /* unused */); 95 if (rc) { 96 EMSG("Error starting secondary hart%"PRIu32, hartid); 97 panic(); 98 } 99 } 100 } 101 #endif 102 103 void init_tee_runtime(void) 104 { 105 call_preinitcalls(); 106 call_early_initcalls(); 107 call_service_initcalls(); 108 109 /* Reinitialize canaries around the stacks with crypto_rng_read(). */ 110 thread_update_canaries(); 111 } 112 113 static bool add_padding_to_pool(vaddr_t va, size_t len, void *ptr __unused) 114 { 115 malloc_add_pool((void *)va, len); 116 return true; 117 } 118 119 static void init_primary(void) 120 { 121 vaddr_t va __maybe_unused = 0; 122 123 /* 124 * Mask asynchronous exceptions before switch to the thread vector 125 * as the thread handler requires those to be masked while 126 * executing with the temporary stack. The thread subsystem also 127 * asserts that the foreign interrupts are blocked when using most of 128 * its functions. 129 */ 130 thread_set_exceptions(THREAD_EXCP_ALL); 131 132 malloc_add_pool(__heap1_start, __heap1_end - __heap1_start); 133 IMSG_RAW("\n"); 134 135 core_mmu_save_mem_map(); 136 core_mmu_init_phys_mem(); 137 boot_mem_foreach_padding(add_padding_to_pool, NULL); 138 va = boot_mem_release_unused(); 139 140 thread_init_threads(CFG_NUM_THREADS); 141 thread_init_primary(); 142 thread_init_per_cpu(); 143 } 144 145 /* May be overridden in plat-$(PLATFORM)/main.c */ 146 __weak void plat_primary_init_early(void) 147 { 148 } 149 150 /* May be overridden in plat-$(PLATFORM)/main.c */ 151 __weak void boot_primary_init_intc(void) 152 { 153 } 154 155 /* May be overridden in plat-$(PLATFORM)/main.c */ 156 __weak void boot_primary_init_core_ids(void) 157 { 158 #ifdef CFG_DT 159 const void *fdt = get_external_dt(); 160 const fdt32_t *reg = NULL; 161 int cpu_offset = 0; 162 int offset = 0; 163 int len = 0; 164 int i = 0; 165 166 offset = fdt_path_offset(fdt, "/cpus"); 167 if (offset < 0) 168 panic("Failed to find /cpus node in the device tree"); 169 170 fdt_for_each_subnode(cpu_offset, fdt, offset) { 171 /* 172 * Assume all TEE cores are enabled. The "reg" 173 * property in the CPU node indicates the hart ID. 174 */ 175 if (fdt_get_status(fdt, cpu_offset) == DT_STATUS_DISABLED) 176 continue; 177 178 reg = fdt_getprop(fdt, cpu_offset, "reg", &len); 179 if (!reg) { 180 EMSG("CPU node does not have 'reg' property"); 181 continue; 182 } 183 184 assert(i < CFG_TEE_CORE_NB_CORE); 185 hartids[i++] = fdt32_to_cpu(*reg); 186 } 187 188 assert(i == CFG_TEE_CORE_NB_CORE); 189 #endif 190 } 191 192 /* May be overridden in plat-$(PLATFORM)/main.c */ 193 __weak void boot_secondary_init_intc(void) 194 { 195 } 196 197 void boot_init_primary_early(void) 198 { 199 init_primary(); 200 } 201 202 void boot_init_primary_late(unsigned long fdt, 203 unsigned long tos_fw_config __unused) 204 { 205 init_external_dt(fdt, CFG_DTB_MAX_SIZE); 206 discover_nsec_memory(); 207 update_external_dt(); 208 thread_init_thread_core_local(CFG_TEE_CORE_NB_CORE); 209 thread_init_boot_thread(); 210 } 211 212 void __weak boot_init_primary_runtime(void) 213 { 214 size_t pos = get_core_pos(); 215 216 /* The primary CPU is always indexed by 0 */ 217 assert(pos == 0); 218 219 IMSG("OP-TEE version: %s", core_v_str); 220 if (IS_ENABLED(CFG_INSECURE)) { 221 IMSG("WARNING: This OP-TEE configuration might be insecure!"); 222 IMSG("WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html"); 223 } 224 IMSG("Primary CPU0 (hart%"PRIu32") initializing", 225 thread_get_hartid_by_hartindex(pos)); 226 boot_primary_init_intc(); 227 boot_primary_init_core_ids(); 228 init_tee_runtime(); 229 boot_mem_release_tmp_alloc(); 230 } 231 232 void __weak boot_init_primary_final(void) 233 { 234 size_t pos = get_core_pos(); 235 236 call_driver_initcalls(); 237 call_finalcalls(); 238 IMSG("Primary CPU0 (hart%"PRIu32") initialized", 239 thread_get_hartid_by_hartindex(pos)); 240 241 #ifdef CFG_RISCV_S_MODE 242 start_secondary_cores(); 243 #endif 244 } 245 246 static void init_secondary_helper(void) 247 { 248 size_t pos = get_core_pos(); 249 250 IMSG("Secondary CPU%zu (hart%"PRIu32") initializing", 251 pos, thread_get_hartid_by_hartindex(pos)); 252 253 /* 254 * Mask asynchronous exceptions before switch to the thread vector 255 * as the thread handler requires those to be masked while 256 * executing with the temporary stack. The thread subsystem also 257 * asserts that the foreign interrupts are blocked when using most of 258 * its functions. 259 */ 260 thread_set_exceptions(THREAD_EXCP_ALL); 261 262 thread_init_per_cpu(); 263 boot_secondary_init_intc(); 264 265 IMSG("Secondary CPU%zu (hart%"PRIu32") initialized", 266 pos, thread_get_hartid_by_hartindex(pos)); 267 } 268 269 void boot_init_secondary(unsigned long nsec_entry __unused) 270 { 271 init_secondary_helper(); 272 } 273