core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@lina

core: add CFG_CALLOUT

Add CFG_CALLOUT with a default value assigned from CFG_CORE_ASYNC_NOTIF
to control if the callout service should be enabled.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: add missing DECLARE_KEEP_PAGER()

Adds missing DECLARE_KEEP_PAGER() for timer_desc, timer_itr_cb(),
arm_cntpct_time_source, wd_ndrv_atomic_cb(), and periodic_callback().
All possibly accessed f

core: add missing DECLARE_KEEP_PAGER()

Adds missing DECLARE_KEEP_PAGER() for timer_desc, timer_itr_cb(),
arm_cntpct_time_source, wd_ndrv_atomic_cb(), and periodic_callback().
All possibly accessed from an interrupt handler and must not be paged.

Fixes: cf707bd0d695 ("core: add callout service")
Fixes: 5b7afacfba96 ("core: arm64: implement timer_init_callout_service()")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-synquacer: use cpu_spin_lock_xsave() and friend

Change RNG PTA implementation for synquacer platform to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead
of call

plat-synquacer: use cpu_spin_lock_xsave() and friend

Change RNG PTA implementation for synquacer platform to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore() instead
of calling thread_mask_exceptions()/cpu_spin_lock() pair and
thread_set_exceptions()/cpu_spin_unlock() pair. This makes the
implementation more consistent.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: mm: use thread_unmask_exceptions() where applicable

Change cache_op_outer() to use thread_unmask_exceptions() instead
of thread_set_exceptions() as the function unmasks interruptions it
p

core: arm: mm: use thread_unmask_exceptions() where applicable

Change cache_op_outer() to use thread_unmask_exceptions() instead
of thread_set_exceptions() as the function unmasks interruptions it
previously masked with thread_set_exceptions(). This change makes the
implementation more consistent.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm: use cpu_spin_lock_xsave() in generic timer implementation

Change generic timer driver for Arm 64bit architecture to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore

core: arm: use cpu_spin_lock_xsave() in generic timer implementation

Change generic timer driver for Arm 64bit architecture to use helper
functions cpu_spin_lock_xsave() and cpu_spin_unlock_xrestore()
instead of calling thread_mask_exceptions()/cpu_spin_lock() pair
and thread_set_exceptions()/cpu_spin_unlock() pair. This makes
the implementation more consistent with the rest of the source tree.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome

plat-vexpress: qemu_armv8: define IT_SEC_PHY_TIMER

Define the interrupt ID of the secure physical timer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service usi

plat-vexpress: initialize callout service

If physical timer interrupt is defined, IT_SEC_PHY_TIMER, and OP-TEE
isn't virtualized, CFG_CORE_SEL2_SPMC isn't defined, initialize the
callout service using that interrupt ID.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: implement timer_init_callout_service()

Implement timer_init_callout_service() needed to initialize and drive
the callout service. Only available in AArch64.

Signed-off-by: Jens Wikland

core: arm64: implement timer_init_callout_service()

Implement timer_init_callout_service() needed to initialize and drive
the callout service. Only available in AArch64.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: add {read,write}_cntps_cval()

Add read_cntps_cval() and write_cntps_cval() to access CNTPS_CVAL_EL1,
Counter-timer Physical Secure Timer CompareValue register.

Signed-off-by: Jens Wikl

core: arm64: add {read,write}_cntps_cval()

Add read_cntps_cval() and write_cntps_cval() to access CNTPS_CVAL_EL1,
Counter-timer Physical Secure Timer CompareValue register.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-synquacer: add initialization value to local variables

Add missing initialization value to local variables in synquacer
platform RNG driver to better comply with OP-TEE OS coding style
and prev

plat-synquacer: add initialization value to local variables

Add missing initialization value to local variables in synquacer
platform RNG driver to better comply with OP-TEE OS coding style
and prevent developers from being confused when using this example
as a example.

No functional change.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architec

core: kernel: factorize delay and timeout implementation

Factorize RISC-V and Arm architectures implementation of delay and
timeout API functions into generic core kernel source directory.

Architecture or platform only need to implement timer tick count
read function delay_cnt_read() and timer tick frequency (in Hertz)
delay_cnt_freq() which is related to CFG_CORE_HAS_GENERIC_TIMER support.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/m

plat-vexpress: disable PL011-specific code when CFG_SEMIHOSTING_CONSOLE=y

When the semihosting console is enabled (with CFG_SEMIHOSTING=y
CFG_SEMIHOSTING_CONSOLE=y) then some code in plat-vexpress/main.c
doesn't make sense and needs to be disabled.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: arm64: implement __do_semihosting() for Aarch64

Implement __do_semihosting() as documented in the "Semihosting for
Aarch32 and Aarch64" specification [1].

Link: https://github.com/ARM-softwar

core: arm64: implement __do_semihosting() for Aarch64

Implement __do_semihosting() as documented in the "Semihosting for
Aarch32 and Aarch64" specification [1].

Link: https://github.com/ARM-software/abi-aa/blob/2023Q3/semihosting/semihosting.rst [1]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: imx: enable TZC380 driver for all i.mx8m socs

This enables the TrustZone Address Space Controller (TZ380) driver for
all members of the i.MX8M soc family. Enabling the driver ensures
protectio

core: imx: enable TZC380 driver for all i.mx8m socs

This enables the TrustZone Address Space Controller (TZ380) driver for
all members of the i.MX8M soc family. Enabling the driver ensures
protection of the OP-TEE memory regions, so that only the secure world
can access it.

Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Sahil Malhotra <sahil.malhotra@nxp.com>

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dts: at91: add device trees for sama7g54_ek

Add the header file for pin definitions.
Add dtsi & dts files for sama7g54_ek.

Signed-off-by: Tony Han <tony.han@microchip.com>
[TP: Update device trees

dts: at91: add device trees for sama7g54_ek

Add the header file for pin definitions.
Add dtsi & dts files for sama7g54_ek.

Signed-off-by: Tony Han <tony.han@microchip.com>
[TP: Update device trees for sama7g54_ek according kernel dtsi and
dts files for the sama7g54_ek.]
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: sama5d2: add huk node for the NVMEM hardware unique key

Add the definition of the NVMEM HUK controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acke

dts: sama5d2: add huk node for the NVMEM hardware unique key

Add the definition of the NVMEM HUK controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: sama5d2: add NVMEM die_id node

Add the definition of the NVMEM die id controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier

dts: sama5d2: add NVMEM die_id node

Add the definition of the NVMEM die id controller in the sama5d2
device tree.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: enable NVMEM unique hardware key and die id support

Enable NVMEM support to allow reading hardware unique key from
the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Sign

plat-sam: enable NVMEM unique hardware key and die id support

Enable NVMEM support to allow reading hardware unique key from
the fuses.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console

core: Refactor console_init() and introduce plat_console_init()

Since there are some cross-platform console drivers, we let
console_init() be common code to have a chance to initialize those
console drivers (e.g., semihosting console).

If the cross-platform console drivers are not configured to be compiled,
plat_console_init() will be invoked to initialize platform-specific
console driver.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-sam: implement plat_get_freq() for sama7g5

Sama7g5 platform does not have support for the ARM generic timer
extension, so plat_get_freq() needs to be updated to be able to
probe clocks early us

plat-sam: implement plat_get_freq() for sama7g5

Sama7g5 platform does not have support for the ARM generic timer
extension, so plat_get_freq() needs to be updated to be able to
probe clocks early using the device tree as for the sama5d2.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: register additional sama7g5 clocks for SCMI usage

- Add the macro definitions for each SCMI clock.
- Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Thomas Perrot <thomas

plat-sam: register additional sama7g5 clocks for SCMI usage

- Add the macro definitions for each SCMI clock.
- Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-sam: register sama7g5 clocks for SCMI usage

Add the macro definitions for each SCMI clock.
Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Ac

plat-sam: register sama7g5 clocks for SCMI usage

Add the macro definitions for each SCMI clock.
Add the table of PMC-SCMI map for sama7g5 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp2: add pm support on stm32mp25

Add support of low power mode on stm32mp25 and perform the needed OP-TEE
bookkeeping before PSCI executes a power management sequence, with the 3
hooks cal

plat-stm32mp2: add pm support on stm32mp25

Add support of low power mode on stm32mp25 and perform the needed OP-TEE
bookkeeping before PSCI executes a power management sequence, with the 3
hooks called by TF-A SPD :
- thread_system_off_handler()
- thread_cpu_resume_handler()
- thread_cpu_suspend_handler()

On PSCI system off request, the STPMIC25 driver need to configure the
regulators properly to handle the always on domain with the board
configuration (PMIC switch OFF, with coin cell, or standby DDR off).

For PSCI suspend requests, the STM32MP25 family supports 5 power levels
in the PSCI topology to handle the regulators configuration done in STPMIC2
for low poser modes, in particular to differentiate the tension for LP and
the LPLV modes:

power level (System mode for a0= Max power level powered down)
--------------------------------------------------------------------------
0: CPU1 core#0 or core#1 (Stop1 or LP-Stop1)
1: D1 domain (LPLV-Stop1)
2: LPLV D1 (Stop2 or LP-Stop2)
3: D2 (LPLV-Stop2)
4: LPLV D2 (Standby)
5: MAX (PowerOff: Standby or VBat)

The hook calls pm_change_state with generic HINT for inform STM32MP25
drivers to operation to performed on suspend/resume:
- PM_HINT_CLOCK_STATE
the IP clock will be deactivated, the pending operation should stop,
cleanup operation can be done on HW to prepare the clock freeze
(optional support by driver)
- PM_HINT_CONTEXT_STATE
called for System level standby when the IP configuration is lost.
The state of each device must be saved in RAM which is preserved
(DDR in self-refresh, mandatory)

Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

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plat-sam: fix static shared memory address and size

Disable the dynamic shared memory allocation that isn't used on SAM
platforms, otherwise the following issue occurs, since the commit
8a6ca1480ddc

plat-sam: fix static shared memory address and size

Disable the dynamic shared memory allocation that isn't used on SAM
platforms, otherwise the following issue occurs, since the commit
8a6ca1480ddc ("core: arm: get DDR range from embedded DTB"):

I/TC: Embedded DTB found
E/TC:0 0 check_phys_mem_is_outside:409 Non-sec mem (0x20800000:0x1f800000) overlaps map (type 18 0x21400000:0x1000)
E/TC:0 0 Panic at core/mm/core_mmu.c:413 <check_phys_mem_is_outside>
E/TC:0 0 TEE load address @ 0x20000000
E/TC:0 0 Call stack:
E/TC:0 0 0x20005655 print_kernel_stack at core/arch/arm/kernel/unwind_arm32.c:109
E/TC:0 0 0x2001c52d __do_panic at core/kernel/panic.c:80
E/TC:0 0 0x200276c1 check_phys_mem_is_outside at core/mm/core_mmu.c:413
E/TC:0 0 0x2002780f core_mmu_set_discovered_nsec_ddr at core/mm/core_mmu.c:481
E/TC:0 0 0x200050b3 discover_nsec_memory at core/arch/arm/kernel/boot.c:1055
E/TC:0 0 0x20005247 boot_init_primary_late at core/arch/arm/kernel/boot.c:1210
E/TC:0 0 0x200001fc reset_primary at core/arch/arm/kernel/entry_a32.S:532

Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-mediatek: add support for MT7988 SoC

Add OP-TEE support for the MT7988 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by:

plat-mediatek: add support for MT7988 SoC

Add OP-TEE support for the MT7988 SoC.

Signed-off-by: guan-gm.lin <guan-gm.lin@mediatek.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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