| 92870f11 | 13-Jun-2024 |
Imre Kis <imre.kis@arm.com> |
core: ffa: Improve FF-A memory sharing compliance
* Deny memory regions with zero pages * Validate total page count field * Validate total descriptor size including memory regions descriptors * Fix
core: ffa: Improve FF-A memory sharing compliance
* Deny memory regions with zero pages * Validate total page count field * Validate total descriptor size including memory regions descriptors * Fix incorrect FFA_ERROR status codes
Signed-off-by: Imre Kis <imre.kis@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b65298cd | 13-Jun-2024 |
Imre Kis <imre.kis@arm.com> |
core: ffa: Deny unsupported memory sharing operations
Fragmented memory sharing operations and memory sharing where the transaction descriptors are forwarded in a custom buffer are not supported for
core: ffa: Deny unsupported memory sharing operations
Fragmented memory sharing operations and memory sharing where the transaction descriptors are forwarded in a custom buffer are not supported for SP destinations. Return early FFA_ERROR if these conditions are detected. Add CFG_NS_VIRTUALIZATION condition for virt_unset_guest calls in thread_spmc.c as a minor refactoring step.
Signed-off-by: Imre Kis <imre.kis@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 4a88c465 | 23-Apr-2024 |
Imre Kis <imre.kis@arm.com> |
core: ffa: Return transaction type flag in retrieve response
Setting 'Memory management transaction type flag' in memory transaction descriptor when returned in FFA_MEM_RETRIEVE_RESP.
Signed-off-by
core: ffa: Return transaction type flag in retrieve response
Setting 'Memory management transaction type flag' in memory transaction descriptor when returned in FFA_MEM_RETRIEVE_RESP.
Signed-off-by: Imre Kis <imre.kis@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 9223d8a0 | 17-Apr-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
dts: st: add RCC support on stm32mp257f-ev1
Configure the clock tree for stm32mp257f-ev1 board.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etien
dts: st: add RCC support on stm32mp257f-ev1
Configure the clock tree for stm32mp257f-ev1 board.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 2a569a93 | 27-Mar-2023 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
dts: st: enable RCC driver in stm32mp251
Add the RCC node to support clock on stm32mp25 platform.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <eti
dts: st: enable RCC driver in stm32mp251
Add the RCC node to support clock on stm32mp25 platform.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b0323341 | 13-Dec-2023 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
drivers: rstctrl: add reset controller for STM32MP25 platforms
Implement the STM32MP25 reset controller device by embedding it with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.
Signed-off-by: G
drivers: rstctrl: add reset controller for STM32MP25 platforms
Implement the STM32MP25 reset controller device by embedding it with CFG_STM32_RSTCTRL=y and CFG_STM32MP25_RSTCTRL=y.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 3ef177b4 | 13-Dec-2023 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
drivers: stm32_rstctrl: move stm32mp1x controller in stm32mp1_rstcrl.c
This change prepares the STM32MP25 reset controller driver. The binding for the STM32MP25 is different from that of the STM32MP
drivers: stm32_rstctrl: move stm32mp1x controller in stm32mp1_rstcrl.c
This change prepares the STM32MP25 reset controller driver. The binding for the STM32MP25 is different from that of the STM32MP1x, so we will create a stm32mp25_rstcrl.c file. This change factorizes STM32 API functions in stm32_rstcrl.c file for probing and passing platform data.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 28c10f9e | 17-Jun-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
clk: stm32mp25: Introduce STM32MP25 clocks platform
This driver is based on clk-stm32-core API to manage STM32 gates, dividers and muxes.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st
clk: stm32mp25: Introduce STM32MP25 clocks platform
This driver is based on clk-stm32-core API to manage STM32 gates, dividers and muxes.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 11ece294 | 10-Dec-2021 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
plat-stm32mp2: add rcc helper function
Add dedicate include file for RCC to add helper function.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etie
plat-stm32mp2: add rcc helper function
Add dedicate include file for RCC to add helper function.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 9b87942a | 03-Jun-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
plat-stm32mp2: sysconfig: add Safe Reset functionality
Add possibility to manage safely master IP reset. This is managed in SYSCFG safe reset control register (SYSCFG_SAFERSTCR)
Signed-off-by: Gabr
plat-stm32mp2: sysconfig: add Safe Reset functionality
Add possibility to manage safely master IP reset. This is managed in SYSCFG safe reset control register (SYSCFG_SAFERSTCR)
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ef7785ad | 17-Mar-2022 |
Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> |
plat-stm32mp2: add stm32mp25 sysconfig driver
Driver to manage system configuration (sysconf) registers the sysconf are identified by an ID to be able to be adapted for DT.
Signed-off-by: Arnaud Po
plat-stm32mp2: add stm32mp25 sysconfig driver
Driver to manage system configuration (sysconf) registers the sysconf are identified by an ID to be able to be adapted for DT.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| e2d9f64a | 19-Jun-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
plat-stm32mp2: conf: enable shared io driver
Default enable shared io driver for platform stm32mp2.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <e
plat-stm32mp2: conf: enable shared io driver
Default enable shared io driver for platform stm32mp2.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| b432ec14 | 13-Jun-2024 |
Tony Han <tony.han@microchip.com> |
plat-sam: register CPU OPP clock for SCMI usage
Add the definitinon for 'AT91_SCMI_CLK_CPU_OPP'. When the CPU OPP clock is available, add it to SCMI clock list.
Signed-off-by: Tony Han <tony.han@mi
plat-sam: register CPU OPP clock for SCMI usage
Add the definitinon for 'AT91_SCMI_CLK_CPU_OPP'. When the CPU OPP clock is available, add it to SCMI clock list.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| f496f2c4 | 13-Jun-2024 |
Tony Han <tony.han@microchip.com> |
plat-sam: prepare for CPU OPP (Operating Performance Points) support
Initialize clock rates array by parsing the device tree.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carr
plat-sam: prepare for CPU OPP (Operating Performance Points) support
Initialize clock rates array by parsing the device tree.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 932a3e11 | 13-May-2024 |
Tony Han <tony.han@microchip.com> |
dts: at91: add assigned-clock settings for sama7g5 qspi0
Assign QSPI0's clock to SYSPLL GCK 133MHz.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@fos
dts: at91: add assigned-clock settings for sama7g5 qspi0
Assign QSPI0's clock to SYSPLL GCK 133MHz.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 1677a7fb | 18-Jun-2024 |
Gavin Liu <gavin.liu@mediatek.com> |
plat-mediatek: add support to extend MAX_XLAT_TABLE
When using the reserved virtual memory space, it is necessary to increase MAX_XLAT_TABLE based on its size.
Signed-off-by: Gavin Liu <gavin.liu@m
plat-mediatek: add support to extend MAX_XLAT_TABLE
When using the reserved virtual memory space, it is necessary to increase MAX_XLAT_TABLE based on its size.
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dc9fd53b | 14-Jun-2024 |
Jerome Forissier <jerome.forissier@linaro.org> |
arm64.h: fix compile error with Clang
Clang 18.1.6 fails to compile OP-TEE OS with the following error:
CC out/arm/core/arch/arm/kernel/vfp.o In file included from core/arch/arm/kernel/vfp
arm64.h: fix compile error with Clang
Clang 18.1.6 fails to compile OP-TEE OS with the following error:
CC out/arm/core/arch/arm/kernel/vfp.o In file included from core/arch/arm/kernel/vfp.c:6: In file included from core/arch/arm/include/arm.h:137: core/arch/arm/include/arm64.h:455:1: error: expected readable system register 455 | DEFINE_U32_REG_READWRITE_FUNCS(fpcr) | ^ core/arch/arm/include/arm64.h:436:3: note: expanded from macro 'DEFINE_U32_REG_READWRITE_FUNCS' 436 | DEFINE_U32_REG_READ_FUNC(reg) \ | ^ core/arch/arm/include/arm64.h:430:3: note: expanded from macro 'DEFINE_U32_REG_READ_FUNC' 430 | DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) | ^ core/arch/arm/include/arm64.h:417:15: note: expanded from macro 'DEFINE_REG_READ_FUNC_' 417 | asm volatile("mrs %0, " #asmreg : "=r" (val64)); \ | ^ <inline asm>:1:10: note: instantiated into assembly here 1 | mrs x8, fpcr | ^
...and similar ones for fpcr write, as well as fpsr read and write.
Clang 12.0.0 does not have any problem with this code which makes me think that it's a Clang/LLVM issue.
Work around the problem by using the coded system register identifiers S3_3_c4_c4_0 and S3_3_c4_c4_1 instead of fpcr and fpsr, respectively. The values 3-3-4-4-0 and 3-3-4-4-1 are taken from the Arm ARM sections C.5.2.8 and C.5.2.9.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 956c2d50 | 12-Jun-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: fix race condition on TA/PTA/StMM context loading
Fix race condition on creation of a context for single instance TAs, PTAs or StMM application. Such race condition could occur and lead to dup
core: fix race condition on TA/PTA/StMM context loading
Fix race condition on creation of a context for single instance TAs, PTAs or StMM application. Such race condition could occur and lead to duplicated contexts if connected close enough that they are created after tee_ta_init_session() calls tee_ta_init_session_with_context() and before the context are added in the centralized context list.
This is realized by keeping tee_ta_mutex held while tee_ctxes list is looked up for matching a context or a new context is added into that list with its .is_initializing field activated. For that purpose user TA and StMM application initialization function are split in 2 functions, the 2nd one used to finalizes the context creation started in the 1st function.
By the way, add inline description comments and fix indentation issues in uaer_ta.h and remove the inline comment in pseudo_ta.c that refers to TA loading whereas the function relates to PTA contexts creation.
Closes: https://github.com/OP-TEE/optee_os/issues/6801 Suggested-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| fee55718 | 14-May-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: make is_initializing field a generic service context
Replace fields is_initializing from struct user_mode_ctx and struct stmm_ctx with a common new field is_initialing in generic struct tee_ta
core: make is_initializing field a generic service context
Replace fields is_initializing from struct user_mode_ctx and struct stmm_ctx with a common new field is_initialing in generic struct tee_ta_ctx so that it can be used in generic context loading functions for contexts which initialization is done with tee_ta_mutex released.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| eaee88fb | 30-May-2024 |
Harsimran Singh Tungal <harsimransingh.tungal@arm.com> |
core: plat-corstone1000: Remove MMCOMM buffer address
Remove MMCOMM buffer address and mapping, as it is not being used anymore
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
core: plat-corstone1000: Remove MMCOMM buffer address
Remove MMCOMM buffer address and mapping, as it is not being used anymore
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Emekcan Aras <emekcan.aras@arm.com>
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| fdf696b7 | 12-Jun-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: rename tee_mm_shm to core_virt_shm_pool
Rename tee_mm_shm to core_virt_shm_pool to make it clear that it handles virtual memory allocations for shared memory.
Signed-off-by: Jens Wiklander <j
core: rename tee_mm_shm to core_virt_shm_pool
Rename tee_mm_shm to core_virt_shm_pool to make it clear that it handles virtual memory allocations for shared memory.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 9b0ee59d | 12-Jun-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: rename tee_mm_vcore to core_virt_mem_pool
Rename tee_mm_vcore to core_virt_mem_pool to make it clear that it handles virtual memory allocations.
Signed-off-by: Jens Wiklander <jens.wiklander@
core: rename tee_mm_vcore to core_virt_mem_pool
Rename tee_mm_vcore to core_virt_mem_pool to make it clear that it handles virtual memory allocations.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 4bc2c5f0 | 10-Jun-2024 |
Sungbae Yoo <sungbaey@nvidia.com> |
core: kernel: move manifest DT functions to dt.c
This moves functions to handle manifest DT, used as a SP (secure partition) manifest via FF-A interface, to core/kernel/dt.c and their definitions to
core: kernel: move manifest DT functions to dt.c
This moves functions to handle manifest DT, used as a SP (secure partition) manifest via FF-A interface, to core/kernel/dt.c and their definitions to dt.h. manifest DT is dependent with CORE_FFA that depends on CFG_DT, as the same as dt.c.
Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 910441c3 | 20-May-2024 |
Yu Chien Peter Lin <peterlin@andestech.com> |
core: kernel: factor out shared memory boot-time helpers
The static and dynamic shared memory helpers used for boot-time reservation/registration are non-architecture-specific. Moving them into the
core: kernel: factor out shared memory boot-time helpers
The static and dynamic shared memory helpers used for boot-time reservation/registration are non-architecture-specific. Moving them into the generic boot.c file will help avoid duplicated code and improve maintainability.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| e92be0c6 | 23-Feb-2024 |
Alvin Chang <alvinga@andestech.com> |
core: mm: move mobj_dyn_shm.c to mm
To enable RISC-V platforms to utilize dynamic shared memory, relocate the non-architecture-specific mobj_dyn_shm.c to the mm directory.
Signed-off-by: Alvin Chan
core: mm: move mobj_dyn_shm.c to mm
To enable RISC-V platforms to utilize dynamic shared memory, relocate the non-architecture-specific mobj_dyn_shm.c to the mm directory.
Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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